Visible to Intel only — GUID: jhn1548753872645
Ixiasoft
Visible to Intel only — GUID: jhn1548753872645
Ixiasoft
5.5. IOPLL IP Core Ports and Signals
Port Name | Type | Condition | Description | ||||||||||||||||||
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refclk | Input | Required | The reference clock source that drives the I/O PLL. | ||||||||||||||||||
rst | Input | Required | The asynchronous reset port for the output clocks. Drive this port high to reset all output clocks to the value of 0. | ||||||||||||||||||
fbclk | Input | Optional | The external feedback input port for the I/O PLL. The IOPLL IP core creates this port when the I/O PLL is operating in external feedback mode or zero-delay buffer mode. To complete the feedback loop, a board-level connection must connect the fbclk port and the external clock output port of the I/O PLL. |
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fboutclk | Output | Optional | The port that feeds the fbclk port through the mimic circuitry. The fboutclk port is available only if the I/O PLL is in external feedback mode. |
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zdbfbclk | Bidirectional | Optional | The bidirectional port that connects to the mimic circuitry. This port must connect to a bidirectional pin that is placed on the positive feedback dedicated output pin of the I/O PLL. The zdbfbclk port is available only if the I/O PLL is in zero-delay buffer mode. |
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locked | Output | Optional | The IOPLL IP core drives this port high when the PLL acquires lock. The port remains high as long as the I/O PLL is locked. The I/O PLL asserts the locked port when the phases and frequencies of the reference clock and feedback clock are the same or within the lock circuit tolerance. When the difference between the two clock signals exceeds the lock circuit tolerance, the I/O PLL loses lock. | ||||||||||||||||||
refclk1 | Input | Optional | Second reference clock source that drives the I/O PLL for clock switchover feature. | ||||||||||||||||||
extswitch | Input | Optional | Active low signal. Assert the extswitch signal low (1’b0) for at least three clock cycles to manually switch the clock. | ||||||||||||||||||
activeclk | Output | Optional | Output signal to indicate which reference clock source is in used by I/O PLL. | ||||||||||||||||||
clkbad | Output | Optional | Output signal that indicates the status of reference clock source is good or bad. | ||||||||||||||||||
cascade_out | Output | Optional | Output signal that feeds into downstream I/O PLL. | ||||||||||||||||||
adjpllin | Input | Optional | Input signal that feeds from upstream I/O PLL. | ||||||||||||||||||
outclk_[] | Output | Optional | Output clock from I/O PLL. | ||||||||||||||||||
permit_cal | Input | Optional | This is an input port for the downstream I/O PLL. Connect this permit_cal port to the locked output port of the upstream I/O PLL. Connecting this permit_cal port ensures that the cascaded I/O PLLs are calibrated in the correct order. | ||||||||||||||||||
scanclk | Input | Optional | Dynamic phase shift clock that drives the IOPLL IP core dynamic phase shift operation. This port must be connected to a valid clock source. The maximum input clock frequency is 100 MHz. The scanclk port is available only if the option of enable access to dynamic phase shift ports is turned on. |
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phase_en | Input | Optional | Active high signal. Asserts to start the dynamic phase shift operation. phase_en can only be asserted 4 clocks after phase_done assertion. The phase_en port is available only if the option of enable access to dynamic phase shift ports is turned on. |
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updn | Input | Optional | Determines the direction of dynamic phase shift. When updn = 0, phase shift is in negative direction. When updn = 1, phase shift is in positive direction. The updn port is available only if the option of enable access to dynamic phase shift ports is turned on. |
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cntsel[4..0] | Input | Optional |
Determines the counter to be selected to perform dynamic phase shift operation.
The cntsel[4..0] port is available only if the option of enable access to dynamic phase shift ports is turned on. |
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num_phase_shift[2..0] | Input | Optional | Determines the number of phase shifts per dynamic phase shift operation. Up to seven phase shifts per operation are possible. Each phase shift step is equal to 1/8 of I/O PLL VCO period. num_phase_shift must never be set to 0 in DPS mode. The num_phase_shift [2..0] port is available only if the option of enable access to dynamic phase shift ports is turned on. |
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phase_done | Output | Optional | The IOPLL IP core drives this port high for one scanclk cycle after dynamic phase shift operation is complete. The phase_done port is available only if the option of enable access to dynamic phase shift ports is turned on. |