Visible to Intel only — GUID: cvc1548753770320
Ixiasoft
Visible to Intel only — GUID: cvc1548753770320
Ixiasoft
5.4.2. IOPLL IP Core Parameters - Settings Tab
Parameter | Value | Description |
---|---|---|
PLL Bandwidth Preset | Low 11, Medium, or High | Specifies the PLL bandwidth preset setting. The default selection is Medium for fabric-feeding I/O PLL, and Low for I/O bank I/O PLL. |
Lock Threshold Setting | Low Lock Time, Medium Lock Time, or High Lock Time | This setting determines the sensitivity of the I/O PLL when detecting lock. This is a tradeoff between the time it takes to lock and the accuracy of the outclk frequency when locked is first asserted. For applications that require the I/O PLL to lock quickly, Low Lock Time is the best option. The estimated lock times are 30 µs + a × refclk_period, where a is 100, 2048, and 4095 for Low Lock Time, Medium Lock Time, and High Lock Time respectively. |
PLL Auto Reset | On or Off | Automatically self-resets the PLL on loss of lock. |
Create a second input clk ‘refclk1’ | On or Off | Turn on to provide a backup clock attached to your PLL that can switch with your original reference clock. |
Second Reference Clock Frequency 12 | — | Selects the frequency of the second input clock signal. The default value is 100.0 MHz. The minimum and maximum value is dependent on the device used. |
Create an ‘active_clk’ signal to indicate the input clock in use 12 | On or Off | Turn on to create the activeclk output. The activeclk output indicates the input clock which is in use by the PLL. Output signal low indicates refclk and output signal high indicates refclk1. |
Create a ‘clkbad’ signal for each of the input clocks 12 | On or Off | Turn on to create two clkbad outputs, one for each input clock. Output signal low indicates the clock is working and output signal high indicates the clock is not working. |
Switchover Mode 12 | Automatic Switchover, Manual Switchover, or Automatic Switchover with Manual Override | Specifies the switchover mode for design application. The IP supports three switchover modes:
|
Switchover Delay 12 | 0–7 | Adds a specific amount of cycle delay to the switchover process. |
Access to PLL LVDS_CLK/LOADEN output port 11 | Disabled, Enable LVDS_CLK/LOADEN 0, or Enable LVDS_CLK/LOADEN 0 & 1 | Select Enable LVDS_CLK/LOADEN 0 or Enable LVDS_CLK/LOADEN o & 1 to enable the PLL lvds_clk or loaden output port. Enables this parameter in case the PLL feeds an LVDS SERDES block with external PLL. When using the I/O PLL outclk ports with LVDS ports, outclk[0..3] are used for lvds_clk[0,1] and loaden[0,1] ports, outclk4 can be used for coreclk ports. |
Enable access to the PLL DPA output port 11 | On or Off | Turn on to enable the PLL DPA output port. |
Enable access to PLL external clock output port | On or Off | Turn on to enable the PLL external clock output port. |
Specifies which outclk to be used as extclk_out[0] source | C0–C6 (I/O bank) | Specifies the outclk port to be used as extclk_out[0] source. |
Specifies which outclk to be used as extclk_out[1] source | C0–C6 (I/O bank) | Specifies the outclk port to be used as extclk_out[1] source. |