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1. Agilex™ 7 FPGA F-Series and I-Series Clocking and PLL Overview
2. F-Series and I-Series Clocking and PLL Architecture and Features
3. F-Series and I-Series Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. IOPLL Reconfig Intel® FPGA IP Core
7. Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series Archives
8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
3.1. Guidelines: Clock Switchover
3.2. Guidelines: Timing Closure
3.3. Guidelines: Resetting the PLL
3.4. Guidelines: Configuration Constraints
3.5. Guidelines: I/O PLL Reconfiguration
3.6. Clocking Constraints
3.7. IP Core Constraints
3.8. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
6.1. Release Information for IOPLL Reconfig Intel® FPGA IP
6.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core
6.3. IOPLL Reconfig IP Core Reconfiguration Modes
6.4. Avalon® Memory-Mapped Interface Ports in the IOPLL Reconfig IP Core
6.5. Address Bus and Data Bus Settings
6.6. Design Example
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5.4.3. IOPLL IP Core Parameters - Cascading Tab
Parameter | Value | Description |
---|---|---|
Connect to an upstream PLL through Core clock Network Cascading (create a permit_cal input signal) | On or Off | Turn on to create an input port to enable destination (downstream) PLL power-up calibration. Connect source (upstream) PLL locked signal to this input port. |
Create a ‘cascade out’ signal to connect with a downstream PLL 13 | On or Off | Turn on to create the cascade_out port, which indicates that this PLL is a source and connects with a destination (downstream) PLL. |
Connect outclk to a downstream PLL through Core Clock Network Cascading | On or Off | Turn on to configure the PLL as an upstream PLL. Connect (upstream) PLL output clock signal to the refclk port of (downstream) PLL. |
cascade_out source 13 | 0–6 | Specifies which output clock to be used as cascading source. |
Create an adjpllin or cclk signal to connect with an upstream PLL 13 | On or Off | Turn on to create an input port, which indicates that this PLL is a destination and connects with a source (upstream) PLL. |