Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

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ID 683752
Date 4/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Powering Up the Development Kit 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Revision History A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Intel® Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Powering Up the Development Kit x
3.1. Default Settings 3.2. Power Up 3.3. Perform board restore
3.3. Perform board restore x
3.3.1. Restore board System Intel® MAX® 10 with default factory image 3.3.2. Restore board QSPI flash with the default factory image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. Test the functionality of the Development Kits 4.3. Control on-board clock through Clock Controller GUI 4.4. Control on-board power regulator through Power Monitor GUI
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing the Quartus Prime Software 4.1.5. Running the BTS GUI
4.2. Test the functionality of the Development Kits x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The XCVR Tab Status Control PMA Setting Data Type Error Control Run Control 4.2.5. The DDR4 Tab 4.2.6. The SSS Tab 4.2.7. The EEPROM Tab
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and access HPS Debug Access Port by JTAG 5.2. Configure the FPGA device by AS modes (Default Mode) 5.3. Configure the FPGA device by AvST modes 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card 5.4.2. HPS NAND Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID settings in Intel® Quartus® Prime QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Powering Up the Development Kit
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Revision History
A. Development Kit Components
B. Additional Information

4.2.4. The XCVR Tab

The XCVR Tab allows you to run transceivers QSFPDDx8, QSFPx4 and MXP loopback tests on your board. You can run the test using either electrical loopback modules or optical fiber modules. Plug QSFPDD loopback module in U12, plug QSFP loopback module in J12, plug MXP loopback cable in J13 before download transceiver design through BTS GUI. The PRBS traffic is 30 Gbps.

Figure 10. The XCVR Tab

The following sections describe the XCVR tab.

Status

The Status control displays the following status information during the loopback test:
  • PLL lock: Shows the PLL locked or unlocked state
  • Pattern Sync: Shows the pattern synced or not state. The pattern is considered synced when the start of the data sequence is detected.
  • Detail: Shows the PLL lock and pattern sync status.
Figure 11. QSFPDD - PLL and Pattern Status

Control

Use the following controls to select an interface to apply PMA settings, data type and error control:
  • QSFPDD x8
  • QSFP x4
  • MXP

PMA Setting

Allows you to make changes to the PMA parameters that affect the active transceiver interface. The following settings are available for analysis:
  • Serial Loopback: Routes signals between the transmitter and the receiver.
  • VOD: Specifies the voltage output differential of the transmitter buffer.
  • Pre-emphasis tap:
    • Pre-tap 1: Specifies the amount of pre-emphasis on the first pre-tap of the transmitter buffer.
    • Pre-tap 2: Specifies the amount of pre-emphasis on the second pre-tap of the transmitter buffer.
    • Pre-tap 3: Specifies the amount of pre-emphasis on the third pre-tap of the transmitter buffer.
    • Post-tap 1: Specifies the amount of pre-emphasis on the post-tap of the transmitter buffer.
  • Equalizer: Specifies the RX tuning mode for receiver equalizer.
Figure 12. QSFPDD - PMA Setting

Data Type

The Data Type control specifies the type of data pattern contained in the transactions. Select the following available data types for analysis:
  • PRBS7: pseudo-random 7-bit sequences
  • PRBS15: pseudo-random 15-bit sequences
  • PRBS23: pseudo-random 23-bit sequences
  • PRBS31: pseudo-random 31-bit sequences (default)

Error Control

This control displays data errors detected during analysis and allows you to insert errors:
  • Detected Errors: Displays the number of data errors detected in the received bit stream.
  • Inserted Errors: Displays the number of errors inserted into the transmit data stream.
  • Insert: Insert a one-word error into the transmit data stream each time you click the button. Insert Error is only enabled during transaction performance analysis.
  • Clear: Resets the Detected Errors counter and Inserted Errors counter to zeros.

Run Control

  • TX and RX performance bars: Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.
  • Start: This control initiates the loopback tests.
  • Data Rate: Displays the XCVR type and data rate of each channel.
Figure 13. QSFPDD - Data Rate
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