Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

Download PDF
ID 683752
Date 4/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Powering Up the Development Kit 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Revision History A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Intel® Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Powering Up the Development Kit x
3.1. Default Settings 3.2. Power Up 3.3. Perform board restore
3.3. Perform board restore x
3.3.1. Restore board System Intel® MAX® 10 with default factory image 3.3.2. Restore board QSPI flash with the default factory image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. Test the functionality of the Development Kits 4.3. Control on-board clock through Clock Controller GUI 4.4. Control on-board power regulator through Power Monitor GUI
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing the Quartus Prime Software 4.1.5. Running the BTS GUI
4.2. Test the functionality of the Development Kits x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The XCVR Tab 4.2.5. The DDR4 Tab 4.2.6. The SSS Tab 4.2.7. The EEPROM Tab
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and access HPS Debug Access Port by JTAG 5.2. Configure the FPGA device by AS modes (Default Mode) 5.3. Configure the FPGA device by AvST modes 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card 5.4.2. HPS NAND Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID settings in Intel® Quartus® Prime QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Powering Up the Development Kit
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Revision History
A. Development Kit Components
B. Additional Information

A.6. Communication Interfaces

PCIe Slot

The PCIe root port is a PCIe Gen4 x16 port which fans out from Intel Agilex® 7 FPGA F-Series P-tile. This port is designed to meet PCIe Gen4 mother board requirement. System Intel® MAX® 10 acts as the board management controller (BMC) of the development kit. It manages power up reset for both PCIe root port (PCIE_RC_PERSTn) and PCIe end point (PCIE_EP_PERSTn). In FPGA user mode, PCIe root complex design can initiate PCIe link reset through FPGA_GPIO[0] signals.

Table 14.  PCIe Slot
Schematic Signal Name Description
PCIE_EP_PERSTn PCIe endpoint reset
PCIE_RC_WAKEn PCIe wake up
PCIE_RC_REFCLKp/n PCIe reference clock
PCIE_RC_PRSNTn PCIe present
I2C_PCIE_SCL/SDA PCIe I2C bus
PCIE_RC_JTAG_TCK/TMS/TDO/TDI/TRSTn PCIe JTAG bus
PCIE_RC_TXP/N[0:15] Transceiver TX
PCIE_RC_RXP/N[0:15] Transceiver RX

QSFP28

QSFP28 port fans out from Intel Agilex® 7 FPGA F-Series E-tile. All four channels can run up to 30G NRZ and 30G PAM4. Two of them can run up to 58G PAM4. This port supports 2x56G, 4x10G and 4x25G application cases.

Table 15.  QSFP28
Schematic Signal Names Description
QSFP_MODPRSn Module present
QSFP_RESETn Module reset
QSFP_MODSELn Mode select
QSFP_INITMODE Initial mode
QSFP_INTn Interrupt
QSFP_I2C_SCL I2C clock
QSFP_I2C_SDA I2C data
ZQSFP_TXP/N[0:3] Transceiver TX
ZQSFP_RXP/N[0:3] Transceiver RX

QSFPDD

QSFPDD port fans out from Intel Agilex® 7 FPGA F-Series E-tile. All eight channels can run up to 30G NRZ and 30G PAM4. Four of them can run up to 58G PAM4. This port is suitable for 2x56G, 4x10G, 4x25G and 8x25G application cases.

Table 16.  QSFPDD
Schematic Signal Names Description
QSFPDD_MODPRSn Module present
QSFPDD_RESETn Module reset
QSFPDD_MODSELn Mode select
QSFPDD_INITMODE Initial mode
QSFPDD_INTn Interrupt
QSFPDD_I2C_SCL I2C clock
QSFPDD_I2C_SDA I2C data
QSFPDD_TXP/N[0:7] Transceiver TX
QSFDDP_RXP/N[0:7] Transceiver RX

MXP

MXP port fan out from Intel Agilex® 7 FPGA F-Series E-tile. All four channels can run up to 30G NRZ and 30G PAM4. Two of them can run up to 58G PAM4. This port supports SMA to equipment, backplane, different host compliance boards for 1x10G/1x25G/1x56G/2x56G/4x10G/4x25G cases.

Table 17.  MXP
Schematic Signal Names Description
MXP_TXP/N[0:3] Transceiver TX
MXP_RXP/N[0:3] Transceiver RX

10/100/1000M Triple speed ethernet (TSE)

TSE port is using SGMII between 80E1111 PHY and Intel Agilex® 7 FPGA F-Series LVDS I/Os.

Table 18.  10/100/1000M Triple speed ethernet (TSE)
Schematic Signal Names Description
ETH_RSTn PHY reset
ETH_INTn Interrupt
ETH_MDC MDIO clock
ETH_MDIO MDIO data
ETH_SGMII_TXp/n SGMII TX
ETH_SGMII_RXp/n SGMII RX

Serial Buses

SDM I/Os (SDM_IO0/12) and Intel® MAX® 10 I/Os (SDM_I2C_SCL/SDA) share the same I2C bus which talks with Intel Agilex® 7 FPGA core regulators. By default, SDM acts as SmartVID master and system Intel® MAX® 10 act as Power GUI master in this chain.

System Intel® MAX® 10 I/Os (SYSMAX_I2C_SCL/SDA) manages the second I2C bus which access all I2C slaves except Intel Agilex® 7 FPGA core regulators. The slaves include power regulators, temperature monitor, voltage monitor, EEPROM, RTC,oscillator and PLLs.

HPS I/Os (HPS_GPIO30/31) can access these two I2C chains by rework optional resistors.

Intel Agilex® 7 FPGA general I/Os (F2M_I2C_SCL/SDA) talks with system Intel® MAX® 10 and it cannot direct access these two I2C chains.

Intel Agilex® 7 FPGA also manages Ethernet PHY, QSFP28, QSFPDD, SODIMM I2C buses and LMK05028 SPI bus by GPIOs.

Table 19.  I2C Debug Headers
Schematic Signal Name Description
ENPIRION_I2C_SCL/SDA Enpirion I2C header J35
SYSMAX_I2C_SCL/SDA System Intel® MAX® 10 I2C bus header J51
Cleaner_SCL/SDA Debug header for clock cleaner J26
Figure 34. I2C Serial Bus (for the Intel Agilex® 7 DK-SI-AGF014EA and DK-SI-AGF014E3ES Development Kits)
Figure 35. I2C Serial Bus (for the Intel Agilex® 7 DK-SI-AGF014EB Development Kit)
Level Two Title