Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

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ID 683752
Date 4/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Powering Up the Development Kit 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Revision History A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Intel® Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Powering Up the Development Kit x
3.1. Default Settings 3.2. Power Up 3.3. Perform board restore
3.3. Perform board restore x
3.3.1. Restore board System Intel® MAX® 10 with default factory image 3.3.2. Restore board QSPI flash with the default factory image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. Test the functionality of the Development Kits 4.3. Control on-board clock through Clock Controller GUI 4.4. Control on-board power regulator through Power Monitor GUI
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing the Quartus Prime Software 4.1.5. Running the BTS GUI
4.2. Test the functionality of the Development Kits x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The XCVR Tab 4.2.5. The DDR4 Tab 4.2.6. The SSS Tab 4.2.7. The EEPROM Tab
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and access HPS Debug Access Port by JTAG 5.2. Configure the FPGA device by AS modes (Default Mode) 5.3. Configure the FPGA device by AvST modes 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card 5.4.2. HPS NAND Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID settings in Intel® Quartus® Prime QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Powering Up the Development Kit
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Revision History
A. Development Kit Components
B. Additional Information

5.3. Configure the FPGA device by AvST modes

  1. Set SW1 to AvST x32 mode first.
  2. Plug SDM QSPI flash daughter into J11.
  3. Default system Intel® MAX® 10 image support AvST x32 mode only. You should build a corresponding .POF image if you select AvST x8 or AvST x16 configuration mode.
  4. Detect QSPI flash in Programmer and program QSPI flash with factory provided AvST x32 test image file. Power cycle the board, use push button S17 to choose page, and S18 to configure FPGA. LED_D27, LED_28, LED_29 are used to indicate the active page.
    Table 6.  AvST x32 LED Behavior
    LED Page0 (XCVR) Page1 (DDR4) Page2 (SSS) Page3 (GPIO)
    LED_D27 ON OFF OFF OFF
    LED_D28 OFF ON OFF ON
    LED_D29 OFF OFF ON ON
    FPGA_LED_G[0] Blinking Blinking OFF/Blinking ON
    FPGA_LED_G[1] ON OFF OFF/Blinking ON
    FPGA_LED_G[2] ON ON OFF/Blinking ON
    FPGA_LED_G[3] ON OFF Blinking ON
    FPGA_LED_G[4] OFF OFF OFF ON
    FPGA_LED_G[5] OFF OFF OFF ON
    FPGA_LED_G[6] OFF OFF OFF ON
    FPGA_LED_G[7] OFF OFF OFF ON
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