Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

Download PDF
ID 683752
Date 4/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Powering Up the Development Kit 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Revision History A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Intel® Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Powering Up the Development Kit x
3.1. Default Settings 3.2. Power Up 3.3. Perform board restore
3.3. Perform board restore x
3.3.1. Restore board System Intel® MAX® 10 with default factory image 3.3.2. Restore board QSPI flash with the default factory image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. Test the functionality of the Development Kits 4.3. Control on-board clock through Clock Controller GUI 4.4. Control on-board power regulator through Power Monitor GUI
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing the Quartus Prime Software 4.1.5. Running the BTS GUI
4.2. Test the functionality of the Development Kits x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The XCVR Tab 4.2.5. The DDR4 Tab 4.2.6. The SSS Tab 4.2.7. The EEPROM Tab
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and access HPS Debug Access Port by JTAG 5.2. Configure the FPGA device by AS modes (Default Mode) 5.3. Configure the FPGA device by AvST modes 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card 5.4.2. HPS NAND Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID settings in Intel® Quartus® Prime QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Powering Up the Development Kit
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Revision History
A. Development Kit Components
B. Additional Information

4.3. Control on-board clock through Clock Controller GUI

The Clock Controller GUI application can change on-board Si549 programmable oscillators to any customized frequency between 0.2 MHz and 800 MHz. The default clock frequency value is 156.25MHz. It can also change both Si5338K programmable PLLs to any frequency between 0.17 MHz and 710 MHz.

To change LMK05028 input/output frequency plan, you should:
  1. Connect J51.2 to J26.19, J51.1 to J26.17 by duban wires, connect J26.12 to J26.11 by jumper. This set LMK05028 work at I2C mode and put it into I 2 C chain. Ensure SW10.2 is set to ON and SW4.4 is set to OFF.
  2. Generate the register file by using TICS Pro tools and MATLAB Runtime v9.0 (2015b, 64-bit).
  3. Import generated register file into on-board chip through Clock Controller GUI.

The instructions to run Clock Controller GUI are stated in the Running the BTS GUI section. You can also start it using the BTS GUI icon Clock.

The Clock Controller GUI communicates with the system Intel® MAX® 10 device through either USB port CN1 or 10-pin JTAG header J19. Then system Intel® MAX® 10 controls these programmable clock parts through a 2-wire serial bus.

Attention: You cannot run the stand-alone Clock Controller GUI application when the Board Test System (BTS) or Power Monitor GUI is running at the same time.
Figure 17. Clock Controller GUI - Si549
Note:
  • LSDIV: Low Speed Output Divider
  • HSDIV: High Speed Output Divider
  • FBDIV: DSPLL™ Feedback Divider used to set Digital VCO Frequency
Figure 18. Clock Controller GUI - Si5338K

The following sections describe the Clock Controller GUI buttons.

Read: Reads the current frequency setting for the oscillator associated with the active tab.

Default: Sets the frequency for the oscillator associated with the active tab back to its default value. You can also return to the default frequencies by power cycling the board.

Set: Sets the programmable oscillator frequency for the selected clock to the value in the CLKx output controls for the Si5338. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this time. Intel recommends resetting the FPGA logic after changing frequencies.

Figure 19. Clock Controller GUI - LMK05028

Import: Import the register file which is generated for new input/output frequency plan into the on-board LMK05028. Register changes are volatile after power recycle.

Related Information
Level Two Title