Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit User Guide

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ID 683752
Date 4/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Powering Up the Development Kit 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Revision History A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Intel® Quartus® Prime Software and Driver Installation 2.2. Quick Start Guide 2.3. Design Examples
3. Powering Up the Development Kit x
3.1. Default Settings 3.2. Power Up 3.3. Perform board restore
3.3. Perform board restore x
3.3.1. Restore board System Intel® MAX® 10 with default factory image 3.3.2. Restore board QSPI flash with the default factory image
4. Board Test System x
4.1. Setting Up the BTS GUI Running Environment 4.2. Test the functionality of the Development Kits 4.3. Control on-board clock through Clock Controller GUI 4.4. Control on-board power regulator through Power Monitor GUI
4.1. Setting Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Installing the Quartus Prime Software 4.1.5. Running the BTS GUI
4.2. Test the functionality of the Development Kits x
4.2.1. The Configure Menu 4.2.2. The Sys Info Tab 4.2.3. The GPIO Tab 4.2.4. The XCVR Tab 4.2.5. The DDR4 Tab 4.2.6. The SSS Tab 4.2.7. The EEPROM Tab
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and access HPS Debug Access Port by JTAG 5.2. Configure the FPGA device by AS modes (Default Mode) 5.3. Configure the FPGA device by AvST modes 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card 5.4.2. HPS NAND Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID settings in Intel® Quartus® Prime QSF file 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Powering Up the Development Kit
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Revision History
A. Development Kit Components
B. Additional Information

A.3. Clocks

Table 10.  Default Clock Frequency
Schematic Signal Name Default Frequency
FPGA_GPIO_REFCLKp/n0 156.25M
REFCLK_GXEp/n0 156.25M
SI53311_CLKOUT1p/n 156.25M
REFCLK_GXPp/n0 100M
REFCLK_GXPp/n2 100M
PCIE_RC_REFCLKp/n 100M
FPGA_GPIO_REFCLKp/n1 125M
SODIMM_REFCLKp/n 100M
FPGA_OSC_CLK_1 125M
FPGA_GPIO_REFCLK 100M
DDR4_COMP_REFCLKp/n 100M
FPGA_SYSTEM_CLK 100M
REFCLK_GXEp/n2 153.6M
REFCLK_GXEp/n3 184.32M
Cleaner_SYSTEM_P/N 184.32M
referenceclk_2 184.32M
referenceclk_3 153.6M

The LMK05028 device is a high-performance clock generator, jitter cleaner and clock synchronizer with advanced reference clock selection and hitless switching to meet the stringent requirements of communications infrastructure applications. This clock device has two independent PLL cores that can each synchronize or lock to one of four reference clock inputs, and it can generate up to eight output clocks with up to six different frequencies.

Two E-tile transceiver recovery clocks (Cleaner_RECOVERY_p/n [0:1]) feed two of four reference clock inputs, single-end and differential SMA clocks feed other two inputs. LMK05028’s output clocks feed back to E-tile transceiver bank, general I/O banks and SMA connectors. LMK05028 can be set to power down mode by SW4.4.

Intel Agilex® 7 FPGA F-Series manages LMK05028 through general purpose I/Os (Cleaner_GPIO[0:6], Cleaner_INSEL, Cleaner SCL/SDA, Cleaner_status[0:1]). The connection between these general purpose IOs and FPGA can be shut down by SW10.2.

Figure 32. FPGA Clocks
Figure 33. Transceiver Clocks
Level Two Title