Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design Example User Guide

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ID 683747
Date 6/22/2020
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives 3. Document Revision History for Low Latency E-tile 40G Ethernet Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Changing Target Device in Hardware Design Example 1.6. Testing the Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Low Latency E-Tile 40G Ethernet Design Example Registers 2.7. Design Example Interface Signals
2.5. Hardware Testing x
2.5.1. Internal Loopback Test 2.5.2. External Loopback Test
1. Quick Start Guide
2. Design Example Description
A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives
3. Document Revision History for Low Latency E-tile 40G Ethernet Design Example User Guide

2.4. Simulation

The testbench sends traffic through the IP core, exercising the transmit side and receive side of the IP core.
Figure 6.  Low Latency E-Tile 40G Ethernet Design Example Block Diagram

The simulation design example top-level test file is basic_avl_tb_top.sv. This file provides a clock reference clk_ref of 156.25 Mhz to the PHY. It includes a task to send and receive 10 packets.

Table 4.   Low Latency E-Tile 40G Ethernet Core Testbench File Descriptions

File Names

Description

Testbench and Simulation Files
basic_avl_tb_top.sv Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.
basic_avl_tb_top_nc.sv Top-level testbench file compatible with the NCSim simulator.
basic_avl_tb_top_msim.sv Top-level testbench file compatible with the ModelSim* simulator.
Testbench Scripts
run_vsim.do

The Mentor Graphics* ModelSim* script to run the testbench.

run_vcs.sh

The Synopsys* VCS* script to run the testbench.

run_vcsmx.sh

The Synopsys* VCS* MX script (combined Verilog HDL and System Verilog with VHDL) to run the testbench.

run_ncsim.sh

The Cadence NCSim script to run the testbench.

run_xcelium.sh The Cadence Xcelium* script to run the testbench.
The successful test run displays output confirming the following behavior:
  1. Waiting for RX clock to settle
  2. Printing PHY status
  3. Sending 10 packets
  4. Receiving 10 packets
  5. Displaying "Testbench complete."

The following sample output illustrates a successful simulation test run:


#Waiting for RX alignment
#RX deskew locked
#RX lane alignment locked
#TX enabled
#**Sending Packet    1...
#**Sending Packet    2...
#**Sending Packet    3...
#**Sending Packet    4...
#**Sending Packet    5...
#**Sending Packet    6...
#**Sending Packet    7...
#**Received Packet   1...
#**Sending Packet    8...
#**Received Packet   2...
#**Sending Packet    9...
#**Received Packet   3...
#**Sending Packet    10...
#**Received Packet   4...
#**Received Packet   5...
#**Received Packet   6...
#**Received Packet   7...
#**Received Packet   8...
#**Received Packet   9...
#**Received Packet   10... 
#**
#** Testbench complete.
#**
#*****************************************
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