Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design Example User Guide

Download PDF
ID 683747
Date 6/22/2020
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives 3. Document Revision History for Low Latency E-tile 40G Ethernet Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Changing Target Device in Hardware Design Example 1.6. Testing the Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Low Latency E-Tile 40G Ethernet Design Example Registers 2.7. Design Example Interface Signals
2.5. Hardware Testing x
2.5.1. Internal Loopback Test 2.5.2. External Loopback Test
1. Quick Start Guide
2. Design Example Description
A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives
3. Document Revision History for Low Latency E-tile 40G Ethernet Design Example User Guide

2.5.2. External Loopback Test

Run these steps to perform the external loopback test:
  1. Reset the system. 
    sys_reset_digital_analog
  2. Display the clock frequency and PHY status. The rx_clk is set to 312.5 MHz and rx_pcs_ready is set to 1. 
    chkphy_status
  3. Start the packet generator.
    start_pkt_gen
  4. Stop the packet generator. 
    stop_pkt_gen
  5. Review the number of transmitted and received packets.
    chkmac_stats
Level Two Title