Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design Example User Guide

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ID 683747
Date 6/22/2020
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives 3. Document Revision History for Low Latency E-tile 40G Ethernet Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Changing Target Device in Hardware Design Example 1.6. Testing the Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Low Latency E-Tile 40G Ethernet Design Example Registers 2.7. Design Example Interface Signals
2.5. Hardware Testing x
2.5.1. Internal Loopback Test 2.5.2. External Loopback Test
1. Quick Start Guide
2. Design Example Description
A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives
3. Document Revision History for Low Latency E-tile 40G Ethernet Design Example User Guide

1.3. Simulating the Design Example Testbench

You can compile and simulate the design by running a simulation script from the command prompt.
  1. At the command prompt, change the working directory to <design_example_dir>/example_testbench.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator.
    Table 3.  Instructions to Simulate the Testbench
    Simulator Instructions
    ModelSim* In the command line, type vsim -do run_vsim.do.

    If you prefer to simulate without bringing up the ModelSim* GUI, type vsim -c -do run_vsim.do.

    Note: The ModelSim* -AE and ModelSim* -ASE simulators cannot simulate this IP core. You must use another supported ModelSim* simulator such as ModelSim* SE.
    VCS* In the command line, type sh run_vcs.sh
    VCS* MX In the command line, type sh run_vcsmx.sh.

    Use this script when the design contains Verilog HDL and System Verilog with VHDL.

    NCSim In the command line, type sh run_ncsim.sh
    Xcelium* In the command line, type sh run_xcelium.sh
A successful simulation ends with the following message: 
Simulation Passed.
or 
Testbench complete.
After successful completion, you can analyze the results.
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