Early Power Estimator for Intel® Cyclone® 10 LP FPGAs User Guide

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ID 683743
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Early Power Estimator for Intel® Cyclone® 10 LP 2. Setting Up the Early Power Estimator for Intel® Cyclone® 10 LP 3. Early Power Estimator Worksheets for Intel® Cyclone® 10 LP 4. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Cyclone® 10 LP
1. Overview of the Early Power Estimator for Intel® Cyclone® 10 LP x
1.1. Power Model Status 1.2. Document Revision History
2. Setting Up the Early Power Estimator for Intel® Cyclone® 10 LP x
2.1. System Requirements 2.2. Download and Install the Early Power Estimator 2.3. Estimating Power Consumption 2.4. Document Revision History
2.2. Download and Install the Early Power Estimator x
2.2.1. Changing the Macro Security Level in Microsoft Excel* 2003 2.2.2. Changing the Macro Security Level in Microsoft Excel* 2007 2.2.3. Changing the Macro Security Level in Microsoft Excel* 2010
2.3. Estimating Power Consumption x
2.3.1. Estimating Power Consumption Before Starting the FPGA Design 2.3.2. Estimating Power Consumption While Creating the FPGA Design 2.3.3. Estimating Power Consumption After Completing the FPGA Design
2.3.1. Estimating Power Consumption Before Starting the FPGA Design x
2.3.1.1. Entering Information into the Early Power Estimator 2.3.1.2. Manually Entering Values
2.3.2. Estimating Power Consumption While Creating the FPGA Design x
2.3.2.1. Importing a File 2.3.2.2. Generating the Early Power Estimator (EPE) File 2.3.2.3. Importing Data into the Early Power Estimator (EPE) Spreadsheet
3. Early Power Estimator Worksheets for Intel® Cyclone® 10 LP x
3.1. Cyclone® 10 LP EPE - Main Worksheet 3.2. Cyclone® 10 LP EPE - Logic Worksheet 3.3. Cyclone® 10 LP EPE - RAM Worksheet 3.4. Cyclone® 10 LP EPE - DSP Worksheet 3.5. Cyclone® 10 LP EPE - I/O Worksheet 3.6. Cyclone® 10 LP EPE - PLL Worksheet 3.7. Cyclone® 10 LP EPE - Clock Worksheet 3.8. Cyclone® 10 LP EPE - Report Worksheet 3.9. Cyclone® 10 LP EPE - Enpirion Worksheet 3.10. Document Revision History
3.1. Cyclone® 10 LP EPE - Main Worksheet x
3.1.1. Input Parameters 3.1.2. Thermal Power 3.1.3. Power Tree Design 3.1.4. Thermal Analysis
3.1.4. Thermal Analysis x
3.1.4.1. Not Using a Heat Sink 3.1.4.2. Using a Heat Sink
3.8. Cyclone® 10 LP EPE - Report Worksheet x
3.8.1. Static Power and Dynamic Current per Voltage Rail 3.8.2. Power Up Current 3.8.3. Power Breakout for Multiple Voltage Supplies 3.8.4. Power Regulator Settings
4. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Cyclone® 10 LP x
4.1. Toggle Rate 4.2. Airflow 4.3. Temperature 4.4. Heat Sink 4.5. Document Revision History
1. Overview of the Early Power Estimator for Intel® Cyclone® 10 LP
2. Setting Up the Early Power Estimator for Intel® Cyclone® 10 LP
3. Early Power Estimator Worksheets for Intel® Cyclone® 10 LP
4. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Cyclone® 10 LP

2.3.1. Estimating Power Consumption Before Starting the FPGA Design

Table 2.  Advantage and Constraints of Power Estimation before Designing FPGA
Advantage Constraint
You can obtain power estimation before starting your FPGA design.
  • Accuracy depends on your inputs and your estimation of the device resources; where this information may change (during or after your design is complete), your power estimation results may be less accurate.
  • The Early Power Estimator (EPE) spreadsheet uses averages and not the actual design implementation details; for example ALUT input usage and routing. The Power Analyzer has access to the full design details.

To estimate power consumption with the EPE spreadsheet before starting your FPGA design, follow these steps:

  1. On the Main worksheet of the EPE spreadsheet, select the target family, device, and package from the Family, Device, and Package drop-down list.
  2. Enter values for each worksheet in the EPE spreadsheet. Different worksheets in the EPE spreadsheet display different power sections, such as clocks and phase-locked loops (PLLs).
  3. The calculator displays the total estimated power consumption in the Total FPGA and Total SoC (if applicable) cells of the Main worksheet.
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