Early Power Estimator for Intel® Cyclone® 10 LP FPGAs User Guide

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ID 683743
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Early Power Estimator for Intel® Cyclone® 10 LP 2. Setting Up the Early Power Estimator for Intel® Cyclone® 10 LP 3. Early Power Estimator Worksheets for Intel® Cyclone® 10 LP 4. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Cyclone® 10 LP
1. Overview of the Early Power Estimator for Intel® Cyclone® 10 LP x
1.1. Power Model Status 1.2. Document Revision History
2. Setting Up the Early Power Estimator for Intel® Cyclone® 10 LP x
2.1. System Requirements 2.2. Download and Install the Early Power Estimator 2.3. Estimating Power Consumption 2.4. Document Revision History
2.2. Download and Install the Early Power Estimator x
2.2.1. Changing the Macro Security Level in Microsoft Excel* 2003 2.2.2. Changing the Macro Security Level in Microsoft Excel* 2007 2.2.3. Changing the Macro Security Level in Microsoft Excel* 2010
2.3. Estimating Power Consumption x
2.3.1. Estimating Power Consumption Before Starting the FPGA Design 2.3.2. Estimating Power Consumption While Creating the FPGA Design 2.3.3. Estimating Power Consumption After Completing the FPGA Design
2.3.1. Estimating Power Consumption Before Starting the FPGA Design x
2.3.1.1. Entering Information into the Early Power Estimator 2.3.1.2. Manually Entering Values
2.3.2. Estimating Power Consumption While Creating the FPGA Design x
2.3.2.1. Importing a File 2.3.2.2. Generating the Early Power Estimator (EPE) File 2.3.2.3. Importing Data into the Early Power Estimator (EPE) Spreadsheet
3. Early Power Estimator Worksheets for Intel® Cyclone® 10 LP x
3.1. Cyclone® 10 LP EPE - Main Worksheet 3.2. Cyclone® 10 LP EPE - Logic Worksheet 3.3. Cyclone® 10 LP EPE - RAM Worksheet 3.4. Cyclone® 10 LP EPE - DSP Worksheet 3.5. Cyclone® 10 LP EPE - I/O Worksheet 3.6. Cyclone® 10 LP EPE - PLL Worksheet 3.7. Cyclone® 10 LP EPE - Clock Worksheet 3.8. Cyclone® 10 LP EPE - Report Worksheet 3.9. Cyclone® 10 LP EPE - Enpirion Worksheet 3.10. Document Revision History
3.1. Cyclone® 10 LP EPE - Main Worksheet x
3.1.1. Input Parameters 3.1.2. Thermal Power 3.1.3. Power Tree Design 3.1.4. Thermal Analysis
3.1.4. Thermal Analysis x
3.1.4.1. Not Using a Heat Sink 3.1.4.2. Using a Heat Sink
3.8. Cyclone® 10 LP EPE - Report Worksheet x
3.8.1. Static Power and Dynamic Current per Voltage Rail 3.8.2. Power Up Current 3.8.3. Power Breakout for Multiple Voltage Supplies 3.8.4. Power Regulator Settings
4. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Cyclone® 10 LP x
4.1. Toggle Rate 4.2. Airflow 4.3. Temperature 4.4. Heat Sink 4.5. Document Revision History
1. Overview of the Early Power Estimator for Intel® Cyclone® 10 LP
2. Setting Up the Early Power Estimator for Intel® Cyclone® 10 LP
3. Early Power Estimator Worksheets for Intel® Cyclone® 10 LP
4. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Cyclone® 10 LP

3.2. Cyclone® 10 LP EPE - Logic Worksheet

Each row in the Logic worksheet of the Early Power Estimator (EPE) spreadsheet represents a separate design module.

Enter the following parameters for each design module:

  • Number of combinational adaptive look-up tables (ALUTs)
  • Number of flipflops
  • Clock frequency in MHz
  • Toggle percentage
  • Average fanout
Figure 13. Logic Worksheet of the EPE Spreadsheet
Table 8.  Logic Worksheet Information
Column Heading Description
Module Specify a name for each module of the design. This is an optional entry.
#LUTs

Enter the number of look-up tables (LUTs).

This is the “Combinational ALUTs” value from the Quartus® Prime Compilation Report Resource Usage Summary section.

#FFs

Enter the number of flipflops in the module.

This is the sum of “Register ALUTs” and “Dedicated logic registers” from the Quartus® Prime Compilation Report Resource Usage Summary section.

Clock routing power is calculated separately on the Clock worksheet of the EPE spreadsheet.

Clock Freq (MHz)

Enter a clock frequency (in MHz). This value is limited by the maximum frequency specification for the device family.

100 MHz with a 12.5% toggle means that each LUT or flipflop output toggles 12.5 million times per second (100 × 12.5%).

Toggle%

Enter the average percentage of logic toggling on each clock cycle. The toggle percentage ranges from 0 to 100%. Typically, the toggle percentage is 12.5%, which is the toggle percentage of a 16-bit counter. To ensure you do not underestimate the toggle percentage, use a higher toggle percentage. Most logic only toggles infrequently; therefore, toggle rates of less than 50% are more realistic.

For example, a T-flipflop (TFF) with its input tied to VCC has a toggle rate of 100% because its output is changing logic states on every clock cycle. Refer to the 4-Bit Counter Example.

Average Fanout Enter the average number of blocks fed by the outputs of the LUTs and flipflops.
Thermal Power (W)–Routing

This shows the power dissipation due to estimated routing (in watts).

Routing power depends on placement and routing, which is a function of design complexity. The values shown represent the routing power based on experimentation of more than 100 designs.

For detailed analysis based on your design’s routing, use the Quartus® Prime Power Analyzer.

Thermal Power (W)–Block

This shows the power dissipation due to internal toggling of the ALMs (in watts).

Logic block power is a combination of the function implemented and the relative toggle rates of the various inputs. The EPE spreadsheet uses an estimate based on observed behavior across more than 100 real-world designs.

For accurate analysis based on your design’s exact synthesis, use the Quartus® Prime Power Analyzer.

Thermal Power (W)–Total This shows the total power dissipation (in watts). The total power dissipation is the sum of the routing and block power.
User Comments Enter any comments. This is an optional entry.
Figure 14. 4-Bit Counter Example

The first TFF with the cout0 LSB output has a toggle rate of 100% because the signal toggles on every clock cycle. The toggle rate for the second TFF with cout1 output is 50% because the signal only toggles on every two clock cycles. Consequently, the toggle rate for the third TFF with cout2 output and fourth TFF with cout3 output are 25% and 12.5%, respectively. Therefore, the average toggle percentage for this 4-bit counter is (100 + 50 + 25 + 12.5)/4 = 46.875%.

For more information about logic block configurations, refer to the Logic Array Blocks and Adaptive Logic Modules section of the Cyclone® 10 LP device handbook.

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