Early Power Estimator for Intel® Cyclone® 10 LP FPGAs User Guide

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ID 683743
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Early Power Estimator for Intel® Cyclone® 10 LP 2. Setting Up the Early Power Estimator for Intel® Cyclone® 10 LP 3. Early Power Estimator Worksheets for Intel® Cyclone® 10 LP 4. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Cyclone® 10 LP
1. Overview of the Early Power Estimator for Intel® Cyclone® 10 LP x
1.1. Power Model Status 1.2. Document Revision History
2. Setting Up the Early Power Estimator for Intel® Cyclone® 10 LP x
2.1. System Requirements 2.2. Download and Install the Early Power Estimator 2.3. Estimating Power Consumption 2.4. Document Revision History
2.2. Download and Install the Early Power Estimator x
2.2.1. Changing the Macro Security Level in Microsoft Excel* 2003 2.2.2. Changing the Macro Security Level in Microsoft Excel* 2007 2.2.3. Changing the Macro Security Level in Microsoft Excel* 2010
2.3. Estimating Power Consumption x
2.3.1. Estimating Power Consumption Before Starting the FPGA Design 2.3.2. Estimating Power Consumption While Creating the FPGA Design 2.3.3. Estimating Power Consumption After Completing the FPGA Design
2.3.1. Estimating Power Consumption Before Starting the FPGA Design x
2.3.1.1. Entering Information into the Early Power Estimator 2.3.1.2. Manually Entering Values
2.3.2. Estimating Power Consumption While Creating the FPGA Design x
2.3.2.1. Importing a File 2.3.2.2. Generating the Early Power Estimator (EPE) File 2.3.2.3. Importing Data into the Early Power Estimator (EPE) Spreadsheet
3. Early Power Estimator Worksheets for Intel® Cyclone® 10 LP x
3.1. Cyclone® 10 LP EPE - Main Worksheet 3.2. Cyclone® 10 LP EPE - Logic Worksheet 3.3. Cyclone® 10 LP EPE - RAM Worksheet 3.4. Cyclone® 10 LP EPE - DSP Worksheet 3.5. Cyclone® 10 LP EPE - I/O Worksheet 3.6. Cyclone® 10 LP EPE - PLL Worksheet 3.7. Cyclone® 10 LP EPE - Clock Worksheet 3.8. Cyclone® 10 LP EPE - Report Worksheet 3.9. Cyclone® 10 LP EPE - Enpirion Worksheet 3.10. Document Revision History
3.1. Cyclone® 10 LP EPE - Main Worksheet x
3.1.1. Input Parameters 3.1.2. Thermal Power 3.1.3. Power Tree Design 3.1.4. Thermal Analysis
3.1.4. Thermal Analysis x
3.1.4.1. Not Using a Heat Sink 3.1.4.2. Using a Heat Sink
3.8. Cyclone® 10 LP EPE - Report Worksheet x
3.8.1. Static Power and Dynamic Current per Voltage Rail 3.8.2. Power Up Current 3.8.3. Power Breakout for Multiple Voltage Supplies 3.8.4. Power Regulator Settings
4. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Cyclone® 10 LP x
4.1. Toggle Rate 4.2. Airflow 4.3. Temperature 4.4. Heat Sink 4.5. Document Revision History
1. Overview of the Early Power Estimator for Intel® Cyclone® 10 LP
2. Setting Up the Early Power Estimator for Intel® Cyclone® 10 LP
3. Early Power Estimator Worksheets for Intel® Cyclone® 10 LP
4. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Cyclone® 10 LP

3.4. Cyclone® 10 LP EPE - DSP Worksheet

Each row in the DSP section represents a DSP design module where all instances of the module have the same configuration, clock frequency, toggle percentage, and register usage. If some (or all) DSP or multiplier instances have different configurations, you must enter the information in different rows.

Specify the following information for each DSP or multiplier module:

  • Configuration
  • Number of instances
  • Clock frequency (in MHz)
  • Toggle percentage of the data outputs
  • Inputs and outputs that are registered or not
  • Module pipelined or not
  • Coefficient
  • Registered Stages
Figure 16. DSP Worksheet of the EPE Spreadsheet
Table 10.  DSP Worksheet Information
Column Heading Description
Module Enter a name for the DSP module in this column. This is an optional value.
Configuration Select the DSP block configuration for the module.
# of Instances

Enter the number of DSP block instances that have the same configuration, clock frequency, toggle percentage, and register usage. This value is independent of the number of dedicated DSP blocks you use.

For example, it is possible to use four 9 × 9 simple multipliers that are implemented in the same DSP block in the FPGA devices. In this case, the number of instances would be four.

To determine the maximum number of instances you can fit in the device for any particular mode, follow these steps:
  1. Open the “DSP Blocks”, “Variable Precision DSP Blocks”, or “Embedded Multipliers” chapter of the respective device handbook.
  2. In the “Number of DSP Blocks” table, take the maximum number of DSP blocks available in the device for the mode of operation.
  3. Divide the maximum number by the “# of Mults” for that mode of operation from the “DSP Block Operation Modes” table.
  4. Use the resulting value for the “# of Instances” in the EPE spreadsheet.
Clock Freq (MHz) Enter the clock frequency for the module in MHz. This value is limited by the maximum frequency specification for the device family.
Toggle %

Enter the average percentage of DSP data outputs toggling on each clock cycle. The toggle percentage ranges from 0 to 50%. The default value is 12.5%. For a more conservative power estimate, use a higher toggle percentage.

In addition, 50% corresponds to a randomly changing signal (because half the time the signal changes from a 0-to-0 or 1-to-1). This is considered the highest meaningful toggle rate for a DSP block.

Reg Inputs?

Select whether the inputs of the dedicated DSP block or multiplier block are registered using the dedicated input registers. If you use the dedicated input registers in the DSP or multiplier block, select Yes. If the inputs are unregistered or registered using registers in the ALMs or the look-up table (LUTs), select No.

Reg Outputs?

Select whether the outputs of the dedicated DSP block or multiplier block are registered using the dedicated input registers. If you use the dedicated output registers in the DSP or multiplier block, select Yes. If the inputs are unregistered or registered using registers in ALMs or LUTs, select No.

Pipelined?

Select whether or not the dedicated DSP block is pipelined. Pipelined DSPs are not available in Cyclone 10 LP devices.

Thermal Power (W)–Routing

This shows the power dissipation due to estimated routing (in watts).

Routing power depends on placement and routing, which is a function of design complexity. The values shown represent the routing power based on experimentation of more than 100 designs.

Thermal Power (W)–Block This shows the estimated power consumed by the DSP blocks (in watts). This value is automatically calculated.
Thermal Power (W)–Total This shows the estimated power (in watts), based on your inputs. It is the total power consumed by the DSP blocks and is equal to the routing power and block power. This value is automatically calculated.
User Comments Enter any comments. This is an optional entry.

For more information about DSP block configurations, refer to DSP Blocks, Variable Precision DSP Blocks, or Embedded Multipliers sections of the Cyclone® 10 LP device handbook.

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