Early Power Estimator for Intel® Cyclone® 10 LP FPGAs User Guide

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ID 683743
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Early Power Estimator for Intel® Cyclone® 10 LP 2. Setting Up the Early Power Estimator for Intel® Cyclone® 10 LP 3. Early Power Estimator Worksheets for Intel® Cyclone® 10 LP 4. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Cyclone® 10 LP
1. Overview of the Early Power Estimator for Intel® Cyclone® 10 LP x
1.1. Power Model Status 1.2. Document Revision History
2. Setting Up the Early Power Estimator for Intel® Cyclone® 10 LP x
2.1. System Requirements 2.2. Download and Install the Early Power Estimator 2.3. Estimating Power Consumption 2.4. Document Revision History
2.2. Download and Install the Early Power Estimator x
2.2.1. Changing the Macro Security Level in Microsoft Excel* 2003 2.2.2. Changing the Macro Security Level in Microsoft Excel* 2007 2.2.3. Changing the Macro Security Level in Microsoft Excel* 2010
2.3. Estimating Power Consumption x
2.3.1. Estimating Power Consumption Before Starting the FPGA Design 2.3.2. Estimating Power Consumption While Creating the FPGA Design 2.3.3. Estimating Power Consumption After Completing the FPGA Design
2.3.1. Estimating Power Consumption Before Starting the FPGA Design x
2.3.1.1. Entering Information into the Early Power Estimator 2.3.1.2. Manually Entering Values
2.3.2. Estimating Power Consumption While Creating the FPGA Design x
2.3.2.1. Importing a File 2.3.2.2. Generating the Early Power Estimator (EPE) File 2.3.2.3. Importing Data into the Early Power Estimator (EPE) Spreadsheet
3. Early Power Estimator Worksheets for Intel® Cyclone® 10 LP x
3.1. Cyclone® 10 LP EPE - Main Worksheet 3.2. Cyclone® 10 LP EPE - Logic Worksheet 3.3. Cyclone® 10 LP EPE - RAM Worksheet 3.4. Cyclone® 10 LP EPE - DSP Worksheet 3.5. Cyclone® 10 LP EPE - I/O Worksheet 3.6. Cyclone® 10 LP EPE - PLL Worksheet 3.7. Cyclone® 10 LP EPE - Clock Worksheet 3.8. Cyclone® 10 LP EPE - Report Worksheet 3.9. Cyclone® 10 LP EPE - Enpirion Worksheet 3.10. Document Revision History
3.1. Cyclone® 10 LP EPE - Main Worksheet x
3.1.1. Input Parameters 3.1.2. Thermal Power 3.1.3. Power Tree Design 3.1.4. Thermal Analysis
3.1.4. Thermal Analysis x
3.1.4.1. Not Using a Heat Sink 3.1.4.2. Using a Heat Sink
3.8. Cyclone® 10 LP EPE - Report Worksheet x
3.8.1. Static Power and Dynamic Current per Voltage Rail 3.8.2. Power Up Current 3.8.3. Power Breakout for Multiple Voltage Supplies 3.8.4. Power Regulator Settings
4. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Cyclone® 10 LP x
4.1. Toggle Rate 4.2. Airflow 4.3. Temperature 4.4. Heat Sink 4.5. Document Revision History
1. Overview of the Early Power Estimator for Intel® Cyclone® 10 LP
2. Setting Up the Early Power Estimator for Intel® Cyclone® 10 LP
3. Early Power Estimator Worksheets for Intel® Cyclone® 10 LP
4. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Cyclone® 10 LP

3.6. Cyclone® 10 LP EPE - PLL Worksheet

Cyclone® 10 LP devices feature PLLs for general use. Each row in the PLL worksheet of the Early Power Estimator (EPE) spreadsheet represents one or more PLLs in the device. Enter the maximum output frequency and the VCO frequency for each PLL. You must also specify whether each PLL is an LVDS, fractional, left/right, or top/bottom PLL.

When a PLL drives source synchronous SERDES hardware, it is referred to as an LVDS PLL. If you are using dedicated transmitters or receivers and are using an LVDS PLL to implement serialization or deserialization, specify an LVDS PLL and enter the power information in the PLL worksheet. LVDS PLLs drive LVDS clock trees and dynamic phase alignment (DPA) buses at the voltage-controlled oscillator (VCO) frequency. If an LVDS PLL drives the LVDS hardware only, enter the appropriate VCO frequency and specify an output frequency of 0 MHz. If the LVDS PLL also drives a clock to a pin or to the core, specify that clock frequency as the output frequency.

Figure 19. PLL Worksheet of the EPE Spreadsheet
Table 13.  PLL Worksheet Information
Column Heading Description
Module Specify a name for the PLL in this column. This is an optional value.
# PLL Blocks Enter the number of PLL blocks with the same specific output frequency and VCO frequency combination.
Output Freq (MHz) Enter the maximum output frequency of the PLL (in MHz). The maximum output frequency is reported in the Output Frequency column of the Quartus II Compilation Report. In the Compilation Report, select Fitter and click Resource Section. Select PLL Usage and click Output Frequency.
VCO Freq (MHz) Enter the internal VCO operating frequency for this module. The LVDS PLL drives the LVDS clock tree and DPA bus at this frequency. This frequency includes the VCO post scale counter.
VCO Freq (MHz) Enter the internal VCO operating frequency for general purpose PLL.
Total Power (W) Shows the estimated combined power for VCCA and VCCD (in watts), based on the maximum output frequency and the VCO frequency you entered. This value is automatically calculated.
User Comments Enter any comments. This is an optional entry.

For more information about the PLLs of the supported device families, refer to the Clock Networks and PLLs section of the Cyclone® 10 LP device handbook.

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