Arria® 10 SoC Boot User Guide

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ID 683735
Date 4/03/2019
Public
Document Table of Contents
Document Table of Contents x
1. Arria 10 SoC Boot User Guide
1. Arria 10 SoC Boot User Guide x
1.1. Boot Process 1.2. Boot Stages 1.3. Boot Devices 1.4. Second-Stage Boot Loader Support Package Generator Tool 1.5. Generating a Boot Loader with an External Flash Boot Device 1.6. Boot and FPGA Configuration 1.7. Boot Debugging 1.8. Appendix A: Building the UEFI Boot Loader 1.9. Revision History for Arria 10 SoC Boot User Guide
1.1. Boot Process x
1.1.1. Typical Boot Flow 1.1.2. Bare Metal Boot Flow 1.1.3. Custom Boot Loader
1.2. Boot Stages x
1.2.1. Reset 1.2.2. First Stage: Boot ROM 1.2.3. Second Stage: Boot Loader (U-Boot)
1.2.2. First Stage: Boot ROM x
1.2.2.1. Boot ROM Flow
1.2.3. Second Stage: Boot Loader (U-Boot) x
1.2.3.1. Second-Stage Boot Flow
1.2.3.1. Second-Stage Boot Flow x
1.2.3.1.1. Typical Boot Flow (Non-Secure) 1.2.3.1.2. Secure Boot Flow
1.3. Boot Devices x
1.3.1. Boot Select 1.3.2. Flash Memory Devices for Booting 1.3.3. Booting From FPGA
1.3.2. Flash Memory Devices for Booting x
1.3.2.1. Quad SPI Flash Devices 1.3.2.2. SD/MMC Flash Devices 1.3.2.3. NAND Flash Devices
1.4. Second-Stage Boot Loader Support Package Generator Tool x
1.4.1. Boot Loader Generation and Flow
1.4.1. Boot Loader Generation and Flow x
1.4.1.1. Step 1: Compiling the FPGA Design 1.4.1.2. Step 2: Hardware Hand-off Files 1.4.1.3. Step 3: Generating the Boot Loader Source 1.4.1.4. Boot Loader Generator Tool: BSP Editor
1.5. Generating a Boot Loader with an External Flash Boot Device x
1.5.1. Prerequisites 1.5.2. Boot Loader Generation Example Using an SD/MMC Controller 1.5.3. Boot Loader Generation Example Using a QSPI Flash Controller 1.5.4. Boot Loader Generation Example Using a NAND Flash Controller
1.7. Boot Debugging x
1.7.1. Cold Boot Debug 1.7.2. Warm Boot Debug 1.7.3. Using the Boot ROM and Boot Loader Debug Registers 1.7.4. Boot Flash Device Issues 1.7.5. HPS Boot Loader Debugging
1.8. Appendix A: Building the UEFI Boot Loader x
1.8.1. Prerequisites 1.8.2. Supported Compiler Toolchains 1.8.3. Obtaining the UEFI Source Code 1.8.4. Compiling the UEFI Source Code with the Linaro Tool Chain 1.8.5. Compiling the UEFI Source Code with the ARM Tool Chain 1.8.6. UEFI Generated Files
1. Arria 10 SoC Boot User Guide

1.8.6. UEFI Generated Files

Compiling the UEFI source code creates the following files in the /data/<username>/pggit/uefi-socfpga/Build/ folder:

Table 8.  UEFI Generated Files
File Description
~ /uefi-socfpga/Build/PEI.256 (256KB)

This file is generated from the mkpimage tool by adding a header to the original file located at ~/uefisocfpga/ Build/Arria10SoCPkg/RELEASE_GCC48/FV/ALTERA_HPS_OCRAM_EFI_ PART1.fd. The file loads directly into the on-chip RAM using DS-5 because it is only 256 KB in size.

This file generates the PEI.ROM file.

~ /uefi-socfpga/Build/PEI.ROM (1MB = 256KB X 4) This file is programmed onto the flash daughter card. The size of this file is four times bigger because the the boot ROM can support up to four backup images. For example, if the first image (256KB) is corrupted, the boot ROM loads the second image and so on.
~ /uefi-socfpga/Build/load_uefi_fw.ds This is the DS-5 script template. It is imported to the DS-5 tool and loads the UEFI firmware for debug and development purposes. This script loads the debug symbols for the user. Currently, it only supports the GCC compiler. ARMCC is not supported.
~ /uefi-socfpga/Build/DXE.ROM This file is currently not in use. Reserved for future use.
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