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1.1. Boot Process
1.2. Boot Stages
1.3. Boot Devices
1.4. Second-Stage Boot Loader Support Package Generator Tool
1.5. Generating a Boot Loader with an External Flash Boot Device
1.6. Boot and FPGA Configuration
1.7. Boot Debugging
1.8. Appendix A: Building the UEFI Boot Loader
1.9. Revision History for Arria 10 SoC Boot User Guide
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1.4.1. Boot Loader Generation and Flow
Generating a boot loader involves several steps to produce a final bootable image.
Each step is dependent on the previous one. Either the associated Intel® Complete Design Suite (ACDS) or SoC EDS tool is used to generate information required for the following dependent steps. See the table below for a list of steps and associated tools:
Steps | Required Tool |
---|---|
Step 1: Compiling the FPGA Design | Quartus® Prime |
Step 2: Identifying the hardware hard processor system (HPS) hand-off files | Quartus® Prime |
Step 3: Generating and building a boot loader source | SoC EDS tool chain and BSP Editor |
The following figure depicts the complete boot loader generation flow using U-Boot.
Note: A similar flow is available for a UEFI boot loader. Refer to the "Appendix A: Building a UEFI Boot Loader" section.
Figure 19. Arria 10 Boot Loader Generation Flow