Stratix® 10 Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

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ID 683718
Date 5/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives A. Document Revision History for Stratix® 10 Low Latency 40G Ethernet Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design Example 1.5. Simulating the Stratix® 10 LL 40GbE Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Stratix® 10 LL 40GbE Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Design Example Interface Signals 2.3. Stratix® 10 LL 40GbE Design Example Registers
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
A. Document Revision History for Stratix® 10 Low Latency 40G Ethernet Design Example User Guide

1.4. Generating the Design Example

Figure 5. Procedure
Figure 6. Example Design Tab in the Stratix® 10 LL 40GbE Parameter Editor

Follow these steps to generate the hardware design example and testbench:

  1. In the Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Quartus® Prime project, or File > Open Project to open an existing Quartus® Prime software project. The wizard prompts you to specify a device family and device.
    Note: The design example overwrites the selection with the device on the target board. You specify the target board from the menu of design example options in the Example Design tab (Step 8). The design example DUT if you select an H-tile device is 1SG280HU3F50E3VGS1, and the design example DUT if you select an L-tile device is 1SG280LU3F50E3VGS1.

  2. In the IP Catalog, locate and select Low Latency 40G Ethernet . The New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. The Quartus® Prime IP parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  4. Click OK. The IP parameter editor appears.
  5. On the IP tab, specify the parameters for your IP core variation.
    Note: The Stratix® 10 LL 40GbE design example does not simulate correctly and does not function correctly if you specify any of the following parameters:
    • Use external TX MAC PLL
    • Enable preamble pass-through turned on
    • Ready latency set to the value of 3
    • Enable TX CRC insertion turned off
  6. On the Example Design tab, under Example Design Files, enable the Simulation option to generate the testbench, and select the Synthesis option to generate the compilation-only and hardware design examples.
    Note: On the Example Design tab, under Generated HDL Format, only Verilog HDL is available. This IP core does not support VHDL.
  7. Under Target Development Kit select the Stratix® 10 GX Transceiver Signal Integrity Development Kit . You must ensure your project targets the specific Stratix® 10 device on the development board.
  8. Click the Generate Example Design button. The Select Example Design Directory window appears.
  9. If you want to modify the design example directory path or name from the defaults displayed (alt_e40_0_example_design ), browse to the new path and type the new design example directory name (<design_example_dir>).
  10. Click OK.
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