Stratix® 10 Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

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ID 683718
Date 5/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives A. Document Revision History for Stratix® 10 Low Latency 40G Ethernet Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design Example 1.5. Simulating the Stratix® 10 LL 40GbE Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Stratix® 10 LL 40GbE Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Design Example Interface Signals 2.3. Stratix® 10 LL 40GbE Design Example Registers
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
A. Document Revision History for Stratix® 10 Low Latency 40G Ethernet Design Example User Guide

1.5. Simulating the Stratix® 10 LL 40GbE Design Example Testbench

Figure 7. Procedure

Follow these steps to simulate the testbench:

  1. Change to the testbench simulation directory <design_example_dir>/example_testbench.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table "Steps to Simulate the Testbench".
  3. Analyze the results. The successful testbench sends ten packets, receives ten packets, and displays "Testbench complete."
    Note: The successful 40GBASE-KR4/CR4 testbench performs auto-negotiation (if enabled) and link training (if enabled) before performing these packet send and receive actions.
    Table 3.  Steps to Simulate the Testbench
    Simulator Instructions
    ModelSim* SE or QuestaSim* or Questa* Intel® FPGA Edition In the command line, type 
    vsim -do run_vsim.do
    If you prefer to simulate without bringing up the ModelSim* GUI, type 
    vsim -c -do run_vsim.do
    Cadence NCSim In the command line, type sh run_ncsim.sh
    Cadence Xcelium* In the command line, type sh run_xcelium.sh
    Synopsys VCS* / VCS* MX In the command line, type sh run_vcs.sh or sh run_vcsmx.sh
    Note: run_vcs.sh is only available if you select Verilog as the Generated HDL Format. If you select VHDL as the Generated HDL Format, you must simulate the testbench with a mixed language simulator using run_vcsmx.sh.

The successful test run displays output confirming the following behavior:

  1. Waiting for RX clock to settle
  2. Printing PHY status
  3. Sending 10 packets
  4. Receiving 10 packets
  5. Displaying "Testbench complete."

The following sample output illustrates a successful simulation test run. For a 40GBASE-KR4/CR4 IP core variation, additional auto-negotiation and link training messages display if these features are enabled. 

#Waiting for RX alignment
#RX deskew locked
#RX lane alignment locked
#TX enabled
#**Sending Packet    1...
#**Sending Packet    2...
#**Sending Packet    3...
#**Sending Packet    4...
#**Sending Packet    5...
#**Sending Packet    6...
#**Sending Packet    7...
#**Received Packet   1...
#**Sending Packet    8...
#**Received Packet   2...
#**Sending Packet    9...
#**Received Packet   3...
#**Sending Packet    10...
#**Received Packet   4...
#**Received Packet   5...
#**Received Packet   6...
#**Received Packet   7...
#**Received Packet   8...
#**Received Packet   9...
#**Received Packet   10... 
#**
#** Testbench complete.
#**
#*****************************************
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