Stratix® 10 Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

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ID 683718
Date 5/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives A. Document Revision History for Stratix® 10 Low Latency 40G Ethernet Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design Example 1.5. Simulating the Stratix® 10 LL 40GbE Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Stratix® 10 LL 40GbE Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Design Example Interface Signals 2.3. Stratix® 10 LL 40GbE Design Example Registers
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
A. Document Revision History for Stratix® 10 Low Latency 40G Ethernet Design Example User Guide

4. Stratix® 10 Low Latency 40GbE IP Core User Guide Archives

IP versions are the same as the Quartus® Prime Design Suite software versions up to v19.1. From Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme. If an IP core version is not listed, the user guide for the previous IP core version applies.
Quartus® Prime Version IP Core Version User Guide
20.3 19.1.0 Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core User Guide
20.2 19.1.0 Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core User Guide
19.3 19.1.0 Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core User Guide
17.1 S10 ES 17.1 S10 ES Low Latency 40-Gbps Ethernet IP Core User Guide 17.1 S10 ES
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