Stratix® 10 Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

ID 683718
Date 5/31/2024
Public

1.6. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Stratix® 10 device, follow these steps:

  1. Ensure hardware design example generation is complete.
  2. In the Intel® Quartus® Prime Pro Edition software, open the Quartus® Prime project <design_example_dir>/hardware_test_design/eth_ex_40 g.qpf.
  3. On the Processing menu, click Start Compilation.
  4. After successful compilation, a SRAM object file (.sof) is available for non-40GBASE-KR4 variations. Follow these steps to program the hardware design example on the Stratix® 10 device:
    1. On the Tools menu, click Programmer.
    2. In the Programmer, click Hardware Setup.
    3. Select a programming device.
    4. Select and add the Stratix® 10 GX Transceiver Signal Integrity Development Kit to which your Quartus® Prime session can connect.
    5. Ensure that Mode is set to JTAG.
    6. Select the Stratix® 10 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    7. In the row with your .sof, check the box for the .sof.
    8. Check the box in the Program/Configure column.
    9. Click Start.