Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 8/28/2023
Public
Document Table of Contents

8.2.4. System Interconnect Slave Properties

The system interconnect connects to various slave interfaces through the main L3 interconnect, the SDRAM L3 interconnect, and the L4 peripheral buses. After reset, all slave interfaces are set to the secure state.

Table 49.  System Interconnect Slave Interfaces

Slave

Interface Width

Clock

Acceptance (Read/Write/Total)13

Security

Privilege

Interface Type

SP Timer 0/1/2/3

32

l4_sp_clk

1/1/1

Boot Secure 14

User Mode

APB* 15

I2C 0/1/2/3/4

32

l4_sp_clk

1/1/1

Boot Secure

User Mode

APB* 15

UART 0/1

32

l4_sp_clk

1/1/1

Boot Secure

User Mode

APB* 15

GPIO 0/1/2

32

l4_sp_clk

1/1/1

Boot Secure

User Mode

APB* 15

SD/MMC CSR

32

l4_mp_clk

1/1/1

Boot Secure

User Mode

APB* 15

EMAC 0/1/2

32

l4_mp_clk

1/1/1

Boot Secure

User Mode

APB* 15

OSC Timer 0/1/2/3

32

l4_sys_free_clk

1/1/1

Secure 16

Privileged

OCP

Watchdog 0/1/2/3

32

l4_sys_free_clk

1/1/1

Secure

Privileged

APB* 15

Clock Manager

32

l4_sys_free_clk

1/1/1

Secure

Privileged

OCP

Reset Manager

32

l4_sys_free_clk

1/1/1

Secure

Privileged

OCP

System Manager

32

l4_sys_free_clk

1/1/1

Secure

Privileged

OCP

FPGA Manager Data

32

l4_sys_free_clk

1/1/1

Secure

Privileged

OCP

FPGA Manager CSR

32

l4_sys_free_clk

1/1/1

Secure

Privileged

OCP

DAP

32

l4_sys_free_clk

1/1/1

Secure

Privileged

APB* 15

DMA Secure CSR

32

l4_main_clk

1/1/1

Boot Secure

User Mode

APB* 15

DMA Non-Secure CSR

32

l4_main_clk

1/1/1

Boot Secure

User Mode

APB* 15

SPI Slave 0/1

32

l4_main_clk

1/1/1

Boot Secure

User Mode

APB* 15

SPI Master 0/1

32

l4_main_clk

1/1/1

Boot Secure

User Mode

APB* 15

USB OTG CSR 0/1

32

l4_mp_clk

1/1/1

Boot Secure

User Mode

AHB*

NAND CSR

32

l4_mp_clk

1/1/1

Boot Secure

User Mode

AHB*

NAND Command and Data

32

l4_mp_clk

1/1/1

Boot Secure

User Mode

AHB*

SD/MMC ECC

32

l4_mp_clk

1/1/2

Secure

Privileged

OCP

On Chip RAM ECC

32

l4_mp_clk

1/1/2

Secure

Privileged

OCP

DMA ECC

32

l4_mp_clk

1/1/2

Secure

Privileged

OCP

NAND ECC

32

l4_mp_clk

1/1/2

Secure

Privileged

OCP

USB OTG ECC

32

l4_mp_clk

1/1/2

Secure

Privileged

OCP

EMACS ECC

32

l4_mp_clk

1/1/2

Secure

Privileged

OCP

ACP

64

mpu_l2ram_clk

13/5/18

Secure

User Mode

AXI*

APB* -DP

32

cs_pl4

1/1/1

Secure

Privileged

APB* 15

DDR

256

f2h_sdram_clk[2:0]

16/16/16

Secure/Non-Secure

User Mode

Avalon

Lightweight HPS-to-FPGA Bridge

32

lwh2fpga_clk

8/8/8

Boot Secure

User Mode

AXI*

HPS-to-FPGA Bridge

128/64/32

hps2fpga_clk

8/8/8

Boot Secure

User Mode

AXI*

On-Chip RAM

64

l3_main_free_clk

2/2/2

Secure/Non-Secure Per 4KB region

User Mode

AXI*

STM

32

cs_at_clk

1/2/2

Secure/Non-Secure

User Mode

AXI*

Note: APB* -DP has no direct connection to the system interconnect.
13 Acceptance is the maximum number of transactions accepted.
14 "Boot Secure" means the slave is in the secure state after reset.
15 The Advanced Peripheral Bus ( APB* ) slave does not support byte enables. All writes must be 32 bits wide.
16 "Secure" means that the slave is permanently in the secure state.