Intel® Arria® 10 Hard Processor System Technical Reference Manual

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ID 683711
Date 8/28/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 Hard Processor System Technical Reference Manual Revision History 2. Introduction to the Hard Processor System 3. Clock Manager 4. Reset Manager 5. FPGA Manager 6. System Manager 7. SoC Security 8. System Interconnect 9. HPS-FPGA Bridges 10. Cortex*-A9 Microprocessor Unit Subsystem 11. CoreSight* Debug and Trace 12. Error Checking and Correction Controller 13. On-Chip Memory 14. NAND Flash Controller 15. SD/MMC Controller 16. Quad SPI Flash Controller 17. DMA Controller 18. Ethernet Media Access Controller 19. USB 2.0 OTG Controller 20. SPI Controller 21. I2C Controller 22. UART Controller 23. General-Purpose I/O Interface 24. Timer 25. Watchdog Timer 26. Hard Processor System I/O Pin Multiplexing 27. Introduction to the HPS Component 28. Instantiating the HPS Component 29. HPS Component Interfaces 30. Simulating the HPS Component A. Booting and Configuration
2. Introduction to the Hard Processor System x
2.1. Features of the HPS 2.2. HPS Block Diagram and System Integration 2.3. Endian Support 2.4. Introduction to the Hard Processor System Address Map
2.2. HPS Block Diagram and System Integration x
2.2.1. HPS Block Diagram 2.2.2. Cortex-A9 MPCore 2.2.3. HPS Interfaces 2.2.4. System Interconnect 2.2.5. On-Chip Memory 2.2.6. Flash Memory Controllers 2.2.7. Support Peripherals 2.2.8. Interface Peripherals 2.2.9. CoreSight Debug and Trace 2.2.10. Hard Processor System I/O Pin Multiplexing
2.2.3. HPS Interfaces x
2.2.3.1. HPS–FPGA Memory-Mapped Interfaces 2.2.3.2. Other HPS Interfaces
2.2.4. System Interconnect x
2.2.4.1. Arria 10 HPS SDRAM L3 Interconnect
2.2.4.1. Arria 10 HPS SDRAM L3 Interconnect x
2.2.4.1.1. SDRAM Adapter 2.2.4.1.2. SDRAM Scheduler
2.2.5. On-Chip Memory x
2.2.5.1. On-Chip RAM 2.2.5.2. Boot ROM
2.2.6. Flash Memory Controllers x
2.2.6.1. NAND Flash Controller 2.2.6.2. Quad SPI Flash Controller 2.2.6.3. SD/MMC Controller
2.2.7. Support Peripherals x
2.2.7.1. Clock Manager 2.2.7.2. Reset Manager 2.2.7.3. Security Manager 2.2.7.4. System Manager 2.2.7.5. System Timers 2.2.7.6. System Watchdog Timers 2.2.7.7. DMA Controller 2.2.7.8. FPGA Manager 2.2.7.9. Error Checking and Correction Controller
2.2.8. Interface Peripherals x
2.2.8.1. EMACs 2.2.8.2. USB Controllers 2.2.8.3. I2C Controllers 2.2.8.4. UARTs 2.2.8.5. SPI Master Controllers 2.2.8.6. SPI Slave Controllers 2.2.8.7. GPIO Interfaces
2.4. Introduction to the Hard Processor System Address Map x
2.4.1. HPS Address Spaces 2.4.2. HPS Peripheral Region Address Map
2.4.1. HPS Address Spaces x
2.4.1.1. SDRAM Address Space 2.4.1.2. MPU Address Space 2.4.1.3. FPGA Slaves Address Space 2.4.1.4. LWFPGA Slaves Address Space 2.4.1.5. L3 Address Space
3. Clock Manager x
3.1. Features of the Clock Manager 3.2. Clock Manager Block Diagram and System Integration 3.3. Functional Description of the Clock Manager 3.4. Clock Manager Address Map and Register Definitions
3.2. Clock Manager Block Diagram and System Integration x
3.2.1. L4 Peripheral Clocks 3.2.2. Boot Clock
3.2.2. Boot Clock x
3.2.2.1. Updating PLL Settings without a System Reset 3.2.2.2. MPU Clock Scaling
3.3. Functional Description of the Clock Manager x
3.3.1. Clock Manager Building Blocks 3.3.2. PLL Integration 3.3.3. Hardware-Managed and Software-Managed Clocks 3.3.4. Hardware Sequenced Clock Groups 3.3.5. Software Sequenced Clocks 3.3.6. Resets 3.3.7. Security 3.3.8. Interrupts
3.3.1. Clock Manager Building Blocks x
3.3.1.1. PLLs 3.3.1.2. FREF, FVCO, and FOUT Equations 3.3.1.3. Clock Gating
4. Reset Manager x
4.1. Reset Manager Block Diagram and System Integration 4.2. Functional Description of the Reset Manager 4.3. Reset Manager Address Map and Register Definitions
4.1. Reset Manager Block Diagram and System Integration x
4.1.1. Reset Controller 4.1.2. Security Reset Functions 4.1.3. Module Reset Signals 4.1.4. Slave Interface and Status Register
4.1.3. Module Reset Signals x
4.1.3.1. Modules Requiring Software Deassert
4.2. Functional Description of the Reset Manager x
4.2.1. Reset Sequencing 4.2.2. Reset Pins 4.2.3. Reset Effects 4.2.4. Reset Handshaking
4.2.1. Reset Sequencing x
4.2.1.1. Cold Reset Assertion Sequence 4.2.1.2. Warm Reset Assertion Sequence 4.2.1.3. Cold and Warm Reset Deassertion Sequence
5. FPGA Manager x
5.1. Features of the FPGA Manager 5.2. FPGA Manager Block Diagram and System Integration 5.3. Functional Description of the FPGA Manager 5.4. FPGA Manager Address Map and Register Definitions
5.3. Functional Description of the FPGA Manager x
5.3.1. FPGA Configuration 5.3.2. FPGA Status 5.3.3. Error Message Extraction 5.3.4. Data AES Decryption 5.3.5. Boot Handshake 5.3.6. General Purpose I/O 5.3.7. Clock 5.3.8. Reset
6. System Manager x
6.1. Features of the System Manager 6.2. System Manager Block Diagram and System Integration 6.3. Functional Description of the System Manager 6.4. System Manager Address Map and Register Definitions
6.3. Functional Description of the System Manager x
6.3.1. Boot Configuration and System Information 6.3.2. Additional Module Control 6.3.3. Boot ROM Code 6.3.4. FPGA Interface Enables 6.3.5. ECC and Parity Control 6.3.6. Preloader Handoff Information 6.3.7. Clocks 6.3.8. Resets
6.3.2. Additional Module Control x
6.3.2.1. DMA Controller 6.3.2.2. NAND Flash Controller 6.3.2.3. EMAC 6.3.2.4. USB 2.0 OTG Controller 6.3.2.5. SD/MMC Controller 6.3.2.6. Watchdog Timer
6.3.3. Boot ROM Code x
6.3.3.1. Controlling the Boot Memory Map Through the System Interconnect
7. SoC Security x
7.1. Security Manager 7.2. Security System Extensions
7.1. Security Manager x
7.1.1. Security Manager Block Diagram 7.1.2. Functional Overview 7.1.3. Functional Description
7.1.3. Functional Description x
7.1.3.1. Secure Initialization Overview 7.1.3.2. Security State 7.1.3.3. Secure Debug 7.1.3.4. Reset Manager 7.1.3.5. Clock Configuration 7.1.3.6. FPGA Security Features 7.1.3.7. Secure Boot 7.1.3.8. Anti-Tamper
7.1.3.1. Secure Initialization Overview x
7.1.3.1.1. Secure Fuses
7.1.3.2. Security State x
7.1.3.2.1. Security Check 7.1.3.2.2. Secure Serial Interface
7.1.3.3. Secure Debug x
7.1.3.3.1. MPU 7.1.3.3.2. JTAG
7.1.3.7. Secure Boot x
7.1.3.7.1. Boot Configuration 7.1.3.7.2. Secure Boot Process 7.1.3.7.3. Authentication and Decryption
7.2. Security System Extensions x
7.2.1. TrustZone* 7.2.2. Arria 10 HPS Secure Firewalls
7.2.1. TrustZone* x
7.2.1.1. Secure Partitioning 7.2.1.2. Virtual Processor Operation
7.2.1.1. Secure Partitioning x
7.2.1.1.1. Secure Bus Accesses 7.2.1.1.2. Secure Cache Accesses
7.2.2. Arria 10 HPS Secure Firewalls x
7.2.2.1. Firewall Diagrams 7.2.2.2. Secure Transaction Protection 7.2.2.3. Privilege Filter 7.2.2.4. Master Security Policy 7.2.2.5. Secure Interconnect Reset
7.2.2.2. Secure Transaction Protection x
7.2.2.2.1. Peripheral and System Firewalls 7.2.2.2.2. HPS-to-FPGA Firewall 7.2.2.2.3. On-Chip RAM Firewall 7.2.2.2.4. SDRAM Firewall
7.2.2.2.1. Peripheral and System Firewalls x
7.2.2.2.1.1. Secure Transaction Example 7.2.2.2.1.2. Non-secure Transaction Configuration
7.2.2.2.3. On-Chip RAM Firewall x
7.2.2.2.3.1. On-Chip RAM Transaction Configuration
8. System Interconnect x
8.1. About the System Interconnect 8.2. Functional Description of the System Interconnect 8.3. Configuring the System Interconnect 8.4. System Interconnect Address Map and Register Definitions
8.1. About the System Interconnect x
8.1.1. Features of the System Interconnect 8.1.2. System Interconnect Block Diagram and System Integration 8.1.3. Arria 10 HPS Secure Firewalls 8.1.4. About the Rate Adapters 8.1.5. About the SDRAM L3 Interconnect 8.1.6. About Arbitration and Quality of Service 8.1.7. About the Service Network 8.1.8. About the Observation Network
8.1.2. System Interconnect Block Diagram and System Integration x
8.1.2.1. System Interconnect Block Diagram 8.1.2.2. Connectivity 8.1.2.3. System Interconnect Architecture
8.1.2.2. Connectivity x
8.1.2.2.1. Arria 10 HPS Master-to-Slave Connectivity Matrix 8.1.2.2.2. On-Chip RAM 8.1.2.2.3. Peripherals Connections 8.1.2.2.4. System Connections 8.1.2.2.5. HPS-to-FPGA Bridge 8.1.2.2.6. SDRAM Connections
8.1.2.3. System Interconnect Architecture x
8.1.2.3.1. SDRAM L3 Interconnect Architecture
8.1.5. About the SDRAM L3 Interconnect x
8.1.5.1. Features of the SDRAM L3 Interconnect 8.1.5.2. SDRAM L3 Interconnect Block Diagram and System Integration 8.1.5.3. About the SDRAM Scheduler
8.2. Functional Description of the System Interconnect x
8.2.1. System Interconnect Address Spaces 8.2.2. Secure Transaction Protection 8.2.3. System Interconnect Master Properties 8.2.4. System Interconnect Slave Properties 8.2.5. System Interconnect Clocks 8.2.6. System Interconnect Resets 8.2.7. Functional Description of the Rate Adapters 8.2.8. Functional Description of the Firewalls 8.2.9. Functional Description of the SDRAM L3 Interconnect 8.2.10. Functional Description of the Arbitration Logic 8.2.11. Functional Description of the QoS Generators 8.2.12. Functional Description of the Observation Network
8.2.1. System Interconnect Address Spaces x
8.2.1.1. Arria 10 HPS Available Address Maps 8.2.1.2. Arria 10 HPS L3 Address Space 8.2.1.3. MPU Address Space 8.2.1.4. SDRAM Address Space 8.2.1.5. Address Remapping
8.2.1.5. Address Remapping x
8.2.1.5.1. Memory Map Remap Bits
8.2.3. System Interconnect Master Properties x
8.2.3.1. Master Caching and Buffering Overrides
8.2.5. System Interconnect Clocks x
8.2.5.1. List of Main L3 Interconnect Clocks 8.2.5.2. List of SDRAM L3 Interconnect Clocks
8.2.8. Functional Description of the Firewalls x
8.2.8.1. Security
8.2.8.1. Security x
8.2.8.1.1. Slave Security 8.2.8.1.2. Master Security
8.2.9. Functional Description of the SDRAM L3 Interconnect x
8.2.9.1. Functional Description of the SDRAM Scheduler 8.2.9.2. Functional Description of the SDRAM Adapter 8.2.9.3. SDRAM L3 Firewalls 8.2.9.4. SDRAM L3 Interconnect Resets
8.2.9.1. Functional Description of the SDRAM Scheduler x
8.2.9.1.1. Monitors for Mutual Exclusion 8.2.9.1.2. Arbitration and Quality of Service in the SDRAM Scheduler
8.2.9.1.1. Monitors for Mutual Exclusion x
8.2.9.1.1.1. Exclusive Access Support
8.2.9.2. Functional Description of the SDRAM Adapter x
8.2.9.2.1. ECC 8.2.9.2.2. SDRAM Adapter Interrupt Support 8.2.9.2.3. SDRAM Adapter Clocks
8.2.9.2.1. ECC x
8.2.9.2.1.1. ECC Write Behavior 8.2.9.2.1.2. ECC Read Behavior
8.2.11. Functional Description of the QoS Generators x
8.2.11.1. QoS Generators in the Interconnect Architecture 8.2.11.2. QoS Mechanisms 8.2.11.3. QoS Generator Modes
8.2.11.2. QoS Mechanisms x
8.2.11.2.1. Packet Urgency 8.2.11.2.2. Pressure Propagation 8.2.11.2.3. Hurry
8.2.11.3. QoS Generator Modes x
8.2.11.3.1. Limiter Mode 8.2.11.3.2. Regulator Mode 8.2.11.3.3. Fixed Mode
8.2.12. Functional Description of the Observation Network x
8.2.12.1. Probes 8.2.12.2. Packet Tracing, Profiling, and Statistics 8.2.12.3. Packet Alarms 8.2.12.4. Error Logging
8.2.12.2. Packet Tracing, Profiling, and Statistics x
8.2.12.2.1. Packet Filtering 8.2.12.2.2. Statistics Collection 8.2.12.2.3. Transaction Profiling
8.2.12.2.3. Transaction Profiling x
8.2.12.2.3.1. Profiling Transaction Latency 8.2.12.2.3.2. Profiling Pending Transactions
8.3. Configuring the System Interconnect x
8.3.1. Configuring the Rate Adapters 8.3.2. Configuring the SDRAM Scheduler 8.3.3. Configuring the Hard Memory Controller 8.3.4. Configuring the Quality of Service Logic
8.3.2. Configuring the SDRAM Scheduler x
8.3.2.1. FPGA Port Configuration 8.3.2.2. Memory Timing Configuration 8.3.2.3. Configuring SDRAM Burst Sizes
8.3.3. Configuring the Hard Memory Controller x
8.3.3.1. SDRAM Adapter Memory Mapped Registers 8.3.3.2. Sharing I/Os between the EMIF and the FPGA
8.3.4. Configuring the Quality of Service Logic x
8.3.4.1. Programming QoS Limiter Mode 8.3.4.2. Programming QoS Regulator Mode 8.3.4.3. Programming QoS Fixed Mode 8.3.4.4. Bandwidth and Saturation 8.3.4.5. QoS Generator Registers 8.3.4.6. QoS Programming Examples
8.3.4.6. QoS Programming Examples x
8.3.4.6.1. Example: One Master Always Takes Precedence 8.3.4.6.2. Example: Tuning for Specific Throughput Requirements
9. HPS-FPGA Bridges x
9.1. Features of the HPS-FPGA Bridges 9.2. Arria 10 HPS-FPGA Bridges Block Diagram and System Integration 9.3. Functional Description of the HPS-FPGA Bridges 9.4. HPS-FPGA Bridges Address Map and Register Definitions for Arria 10
9.3. Functional Description of the HPS-FPGA Bridges x
9.3.1. Functional Description of the FPGA-to-HPS Bridge 9.3.2. Functional Description of the HPS-to-FPGA Bridge 9.3.3. Functional Description of the Lightweight HPS-to-FPGA Bridge 9.3.4. Clocks and Resets 9.3.5. Data Width Sizing
9.3.1. Functional Description of the FPGA-to-HPS Bridge x
9.3.1.1. FPGA-to-HPS Access to ACP 9.3.1.2. FPGA-to-HPS Bridge Slave Signals
9.3.2. Functional Description of the HPS-to-FPGA Bridge x
9.3.2.1. HPS-to-FPGA Bridge Master Signals
9.3.3. Functional Description of the Lightweight HPS-to-FPGA Bridge x
9.3.3.1. Lightweight HPS-to-FPGA Bridge Master Signals
9.3.4. Clocks and Resets x
9.3.4.1. FPGA-to-HPS Bridge Clocks and Resets 9.3.4.2. HPS-to-FPGA Bridge Clocks and Resets 9.3.4.3. Lightweight HPS-to-FPGA Bridge Clocks and Resets 9.3.4.4. Taking HPS-FPGA Bridges Out of Reset
9.3.5. Data Width Sizing x
9.3.5.1. Ready Latency Support
10. Cortex*-A9 Microprocessor Unit Subsystem x
10.1. Features of the Cortex-A9 MPU Subsystem 10.2. Cortex*-A9 MPU Subsystem Block Diagram and System Integration 10.3. Cortex*-A9 MPCore 10.4. L2 Cache 10.5. CPU Prefetch 10.6. TrustZone* 10.7. Debugging Modules 10.8. Clocks 10.9. Cortex*-A9 MPU Subsystem Register Implementation
10.2. Cortex*-A9 MPU Subsystem Block Diagram and System Integration x
10.2.1. Cortex*-A9 MPU Subsystem with System Interconnect 10.2.2. Cortex*-A9 MPU Subsystem Internals
10.3. Cortex*-A9 MPCore x
10.3.1. Functional Description 10.3.2. Implementation Details 10.3.3. Cortex*-A9 Processor 10.3.4. Interactive Debugging Features 10.3.5. L1 Caches 10.3.6. Preload Engine 10.3.7. Floating Point Unit 10.3.8. NEON* Multimedia Processing Engine 10.3.9. Memory Management Unit 10.3.10. Performance Monitoring Unit 10.3.11. Arm* Cortex* -A9 MPCore* Timers 10.3.12. Generic Interrupt Controller 10.3.13. Global Timer 10.3.14. Snoop Control Unit 10.3.15. Accelerator Coherency Port
10.3.3. Cortex*-A9 Processor x
10.3.3.1. Reset
10.3.5. L1 Caches x
10.3.5.1. Cache Latency
10.3.8. NEON* Multimedia Processing Engine x
10.3.8.1. Single Instruction, Multiple Data (SIMD) Processing 10.3.8.2. Features of the NEON* MPE
10.3.9. Memory Management Unit x
10.3.9.1. TLBs Supported By the MMU 10.3.9.2. TLB Features 10.3.9.3. The Boot Region 10.3.9.4. The SDRAM Region 10.3.9.5. The FPGA Slaves Region 10.3.9.6. The HPS Peripherals Region
10.3.9.3. The Boot Region x
10.3.9.3.1. Boot ROM Mapping
10.3.11. Arm* Cortex* -A9 MPCore* Timers x
10.3.11.1. Functional Description 10.3.11.2. Implementation Details
10.3.12. Generic Interrupt Controller x
10.3.12.1. Functional Description 10.3.12.2. Implementation Details
10.3.12.2. Implementation Details x
10.3.12.2.1. GIC Interrupt Map for the Arria 10 SoC HPS
10.3.13. Global Timer x
10.3.13.1. Functional Description 10.3.13.2. Implementation Details
10.3.14. Snoop Control Unit x
10.3.14.1. Functional Description 10.3.14.2. Implementation Details
10.3.14.1. Functional Description x
10.3.14.1.1. Coherent Memory, Snoop Control Unit, and Accelerator Coherency Port
10.3.15. Accelerator Coherency Port x
10.3.15.1. AxUSER and AxCACHE Attributes 10.3.15.2. AxPROT Attributes 10.3.15.3. Cache Coherency for ACP Shared Requests 10.3.15.4. AXI Master Configuration for ACP Access 10.3.15.5. Burst Sizes and Byte Strobes 10.3.15.6. Exclusive and Locked Accesses 10.3.15.7. Avoiding ACP Dependency Lockup
10.3.15.4. AXI Master Configuration for ACP Access x
10.3.15.4.1. Configuring AxCACHE[3:0] Sideband Signals for Coherent Accesses 10.3.15.4.2. Configuring AxUSER[4:0] Sideband Signals 10.3.15.4.3. Configuring AxPROT[2:0] Sideband Signals for Coherent Accesses
10.3.15.5. Burst Sizes and Byte Strobes x
10.3.15.5.1. Recommended Burst Types
10.4. L2 Cache x
10.4.1. Functional Description
10.4.1. Functional Description x
10.4.1.1. Cache Controller Configuration 10.4.1.2. Single Event Upset Protection 10.4.1.3. L2 Cache Parity 10.4.1.4. L2 Cache Lockdown Capabilities 10.4.1.5. L2 Cache Event Monitoring 10.4.1.6. L2 Cache Address Filtering 10.4.1.7. Cache Latency
10.4.1.1. Cache Controller Configuration x
10.4.1.1.1. Implementation Details
10.4.1.1.1. Implementation Details x
10.4.1.1.1.1. L2 Cache Event Monitoring
10.6. TrustZone* x
10.6.1. Secure Partitioning 10.6.2. Virtual Processor Operation 10.6.3. Secure Debug
10.6.1. Secure Partitioning x
10.6.1.1. Secure Bus Accesses 10.6.1.2. Secure Cache Accesses
10.7. Debugging Modules x
10.7.1. Program Trace 10.7.2. Event Trace 10.7.3. Cross-Triggering
10.9. Cortex*-A9 MPU Subsystem Register Implementation x
10.9.1. Cortex*-A9 MPU Subsystem Address Map for Arria 10 10.9.2. L2 Cache Controller Address Map for Arria 10
11. CoreSight* Debug and Trace x
11.1. Features of CoreSight* Debug and Trace 11.2. Arm* CoreSight* Documentation 11.3. CoreSight Debug and Trace Block Diagram and System Integration 11.4. Functional Description of CoreSight Debug and Trace 11.5. CoreSight* Debug and Trace Programming Model 11.6. CoreSight Debug and Trace Address Map and Register Definitions
11.4. Functional Description of CoreSight Debug and Trace x
11.4.1. Debug Access Port 11.4.2. System Trace Macrocell 11.4.3. Trace Funnel 11.4.4. CoreSight Trace Memory Controller 11.4.5. AMBA* Trace Bus Replicator 11.4.6. Trace Port Interface Unit 11.4.7. Embedded Cross Trigger System 11.4.8. Program Trace Macrocell 11.4.9. HPS Debug APB* Interface 11.4.10. FPGA Interface 11.4.11. Debug Clocks 11.4.12. Debug Resets
11.4.1. Debug Access Port x
11.4.1.1. JTAG Connection
11.4.4. CoreSight Trace Memory Controller x
11.4.4.1. Embedded Trace FIFO 11.4.4.2. Embedded Trace Router
11.4.7. Embedded Cross Trigger System x
11.4.7.1. Cross Trigger Interface 11.4.7.2. Cross Trigger Matrix
11.4.10. FPGA Interface x
11.4.10.1. DAP 11.4.10.2. STM 11.4.10.3. FPGA-CTI 11.4.10.4. CTI-NoC 11.4.10.5. TPIU
11.5. CoreSight* Debug and Trace Programming Model x
11.5.1. Coresight Component Address 11.5.2. STM Channels 11.5.3. CTI Trigger Connections to Outside the Debug System 11.5.4. Configuring Embedded Cross-Trigger Connections
11.5.3. CTI Trigger Connections to Outside the Debug System x
11.5.3.1. CTI 11.5.3.2. FPGA-CTI 11.5.3.3. L3-CTI
11.5.4. Configuring Embedded Cross-Trigger Connections x
11.5.4.1. Configuring Trigger Input 0 11.5.4.2. Triggering a Flush of Trace Data to the TPIU 11.5.4.3. Triggering an STM message 11.5.4.4. Triggering a Breakpoint on CPU 1
11.6. CoreSight Debug and Trace Address Map and Register Definitions x
11.6.1. stm Address Map 11.6.2. dap Address Map
12. Error Checking and Correction Controller x
12.1. ECC Controller Features 12.2. ECC Supported Memories 12.3. ECC Controller Block Diagram and System Integration 12.4. ECC Controller Functional Description 12.5. ECC Controller Address Map and Register Descriptions
12.4. ECC Controller Functional Description x
12.4.1. Overview 12.4.2. ECC Structure 12.4.3. Memory Data Initialization 12.4.4. Indirect Memory Access 12.4.5. Error Logging 12.4.6. ECC Controller Interrupts 12.4.7. ECC Controller Initialization and Configuration 12.4.8. ECC Controller Clocks 12.4.9. ECC Controller Reset
12.4.2. ECC Structure x
12.4.2.1. RAM and ECC Memory Organization Example
12.4.4. Indirect Memory Access x
12.4.4.1. Watchdog Timer 12.4.4.2. Data Correction 12.4.4.3. Error Injection 12.4.4.4. Memory Testing 12.4.4.5. Error Checking and Correction Algorithm
12.4.4.4. Memory Testing x
12.4.4.4.1. Peripheral Slave Interface Tests 12.4.4.4.2. Register Interface Tests
12.4.5. Error Logging x
12.4.5.1. Recent Error Address Registers 12.4.5.2. Single-Bit Error Occurrence 12.4.5.3. Single-Bit Error Look-Up Table
12.4.6. ECC Controller Interrupts x
12.4.6.1. Single-Bit Error Interrupts 12.4.6.2. Double-Bit Error Interrupt 12.4.6.3. Interrupt Testing
12.4.6.1. Single-Bit Error Interrupts x
12.4.6.1.1. All Single-Bit Error Interrupt 12.4.6.1.2. LUT Overflow Interrupt 12.4.6.1.3. Counter Match Interrupt
13. On-Chip Memory x
13.1. On-Chip RAM 13.2. Boot ROM 13.3. On-Chip Memory Address Map and Register Definitions
13.1. On-Chip RAM x
13.1.1. Features of the On-Chip RAM 13.1.2. On-Chip RAM Block Diagram and System Integration 13.1.3. Functional Description of the On-Chip RAM
13.1.3. Functional Description of the On-Chip RAM x
13.1.3.1. On-Chip RAM Clocks 13.1.3.2. On-Chip RAM Resets 13.1.3.3. On-Chip RAM Initialization 13.1.3.4. On-Chip RAM Firewall 13.1.3.5. ECC Protection
13.2. Boot ROM x
13.2.1. Features of the Boot ROM 13.2.2. Boot ROM Block Diagram and System Integration 13.2.3. Functional Description of the Boot ROM
13.2.3. Functional Description of the Boot ROM x
13.2.3.1. Boot ROM Clocks 13.2.3.2. Boot ROM Resets
14. NAND Flash Controller x
14.1. NAND Flash Controller Features 14.2. NAND Flash Controller Block Diagram and System Integration 14.3. NAND Flash Controller Signal Descriptions 14.4. Functional Description of the NAND Flash Controller 14.5. NAND Flash Controller Programming Model 14.6. NAND Flash Controller Address Map and Register Definitions
14.4. Functional Description of the NAND Flash Controller x
14.4.1. Discovery and Initialization 14.4.2. Bootstrap Interface 14.4.3. Configuration by Host 14.4.4. Local Memory Buffer 14.4.5. Clocks 14.4.6. Resets 14.4.7. Indexed Addressing 14.4.8. Command Mapping 14.4.9. Data DMA 14.4.10. ECC
14.4.2. Bootstrap Interface x
14.4.2.1. Bootstrap Setting Bits
14.4.3. Configuration by Host x
14.4.3.1. Recommended Bootstrap Settings for 512-Byte Page Device 14.4.3.2. NAND Page Main and Spare Areas
14.4.5. Clocks x
14.4.5.1. Clock Generation 14.4.5.2. Clock Enable 14.4.5.3. Clock Switching
14.4.6. Resets x
14.4.6.1. Taking the NAND Flash Controller Out of Reset
14.4.7. Indexed Addressing x
14.4.7.1. Register Map for Indexed Addressing 14.4.7.2. Indexed Addressing Host Usage
14.4.8. Command Mapping x
14.4.8.1. MAP00 Commands 14.4.8.2. MAP01 Commands 14.4.8.3. MAP10 Commands 14.4.8.4. MAP11 Commands
14.4.8.1. MAP00 Commands x
14.4.8.1.1. MAP00 Command Format 14.4.8.1.2. MAP00 Usage Limitations
14.4.8.2. MAP01 Commands x
14.4.8.2.1. MAP01 Command Format 14.4.8.2.2. MAP01 Usage Limitations
14.4.8.3. MAP10 Commands x
14.4.8.3.1. MAP10 Command Format 14.4.8.3.2. MAP10 Operations 14.4.8.3.3. MAP10 Usage Limitations
14.4.8.4. MAP11 Commands x
14.4.8.4.1. MAP11 Control Format 14.4.8.4.2. MAP11 Usage Limitations
14.4.9. Data DMA x
14.4.9.1. Multi-Transaction DMA Command 14.4.9.2. Burst DMA Command
14.4.9.1. Multi-Transaction DMA Command x
14.4.9.1.1. Command-Data Pair Formats 14.4.9.1.2. Using Multi-Transaction DMA Commands
14.4.10. ECC x
14.4.10.1. Correction Capability, Sector Size, and Check Bit Size 14.4.10.2. ECC Programming Modes 14.4.10.3. Preserving Bad Block Markers 14.4.10.4. Error Correction Status
14.4.10.2. ECC Programming Modes x
14.4.10.2.1. Main Area Transfer Mode 14.4.10.2.2. Spare Area Transfer Mode 14.4.10.2.3. Main+Spare Area Transfer Mode
15. SD/MMC Controller x
15.1. Features of the SD/MMC Controller 15.2. SD/MMC Controller Block Diagram and System Integration 15.3. SD/MMC Controller Signal Description 15.4. Functional Description of the SD/MMC Controller 15.5. SD/MMC Controller Programming Model 15.6. SD/MMC Controller Address Map and Register Definitions
15.1. Features of the SD/MMC Controller x
15.1.1. SD Card Support Matrix 15.1.2. MMC Support Matrix
16. Quad SPI Flash Controller x
16.1. Features of the Quad SPI Flash Controller 16.2. Quad SPI Flash Controller Block Diagram and System Integration 16.3. Quad SPI Flash Controller Signal Description 16.4. Functional Description of the Quad SPI Flash Controller 16.5. Quad SPI Flash Controller Programming Model 16.6. Quad SPI Flash Controller Address Map and Register Definitions
16.4. Functional Description of the Quad SPI Flash Controller x
16.4.1. Overview 16.4.2. Data Slave Interface 16.4.3. SPI Legacy Mode 16.4.4. Register Slave Interface 16.4.5. Local Memory Buffer 16.4.6. DMA Peripheral Request Controller 16.4.7. Arbitration between Direct/Indirect Access Controller and STIG 16.4.8. Configuring the Flash Device 16.4.9. XIP Mode 16.4.10. Write Protection 16.4.11. Data Slave Sequential Access Detection 16.4.12. Clocks 16.4.13. Resets 16.4.14. Interrupts
16.4.2. Data Slave Interface x
16.4.2.1. Direct Access Mode 16.4.2.2. Indirect Access Mode
16.4.2.1. Direct Access Mode x
16.4.2.1.1. Data Slave Remapping Example 16.4.2.1.2. AHB*
16.4.2.2. Indirect Access Mode x
16.4.2.2.1. Indirect Read Operation 16.4.2.2.2. Indirect Write Operation 16.4.2.2.3. Consecutive Reads and Writes
16.4.4. Register Slave Interface x
16.4.4.1. STIG Operation
16.4.8. Configuring the Flash Device x
16.4.8.1. Write Request
16.4.12. Clocks x
16.4.12.1. Clock Gating
16.4.13. Resets x
16.4.13.1. Taking the Quad SPI Flash Controller Out of Reset 16.4.13.2. SRAM Initialization Procedure with ECC Enabled
16.5. Quad SPI Flash Controller Programming Model x
16.5.1. Setting Up the Quad SPI Flash Controller 16.5.2. Indirect Read Operation with DMA Disabled 16.5.3. Indirect Read Operation with DMA Enabled 16.5.4. Indirect Write Operation with DMA Disabled 16.5.5. Indirect Write Operation with DMA Enabled 16.5.6. XIP Mode Operations
16.5.6. XIP Mode Operations x
16.5.6.1. Entering XIP Mode 16.5.6.2. Exiting XIP Mode 16.5.6.3. XIP Mode at Power on Reset
16.5.6.1. Entering XIP Mode x
16.5.6.1.1. Micron Quad SPI Flash Devices with Support for Basic-XIP 16.5.6.1.2. Micron Quad SPI Flash Devices without Support for Basic-XIP 16.5.6.1.3. Winbond Quad SPI Flash Devices 16.5.6.1.4. Spansion Quad SPI Flash Devices
17. DMA Controller x
17.1. Features of the DMA Controller 17.2. DMA Controller Block Diagram and System Integration 17.3. Functional Description of the DMA Controller 17.4. DMA Controller Address Map and Register Definitions
17.3. Functional Description of the DMA Controller x
17.3.1. Peripheral Request Interface
17.3.1. Peripheral Request Interface x
17.3.1.1. Peripheral Request Interface Mapping
17.4. DMA Controller Address Map and Register Definitions x
17.4.1. DMA Controller Address Map and Register Definitions
18. Ethernet Media Access Controller x
18.1. Features of the Ethernet MAC 18.2. EMAC Block Diagram and System Integration 18.3. EMAC Signal Description 18.4. EMAC Internal Interfaces 18.5. Functional Description of the EMAC 18.6. Ethernet MAC Programming Model 18.7. Ethernet MAC Address Map and Register Definitions
18.1. Features of the Ethernet MAC x
18.1.1. MAC 18.1.2. DMA 18.1.3. Management Interface 18.1.4. Acceleration 18.1.5. PHY Interface
18.3. EMAC Signal Description x
18.3.1. HPS EMAC I/O Signals 18.3.2. FPGA EMAC I/O Signals 18.3.3. PHY Management Interface
18.3.3. PHY Management Interface x
18.3.3.1. MDIO Interface 18.3.3.2. I2C External PHY Management Interface
18.4. EMAC Internal Interfaces x
18.4.1. DMA Master Interface 18.4.2. Timestamp Interface 18.4.3. System Manager Configuration Interface
18.6. Ethernet MAC Programming Model x
18.6.1. System Level EMAC Configuration Registers 18.6.2. EMAC FPGA Interface Initialization 18.6.3. EMAC HPS Interface Initialization 18.6.4. DMA Initialization 18.6.5. EMAC Initialization and Configuration 18.6.6. Performing Normal Receive and Transmit Operation 18.6.7. Stopping and Starting Transmission 18.6.8. Programming Guidelines for Energy Efficient Ethernet 18.6.9. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output
18.6.8. Programming Guidelines for Energy Efficient Ethernet x
18.6.8.1. Entering and Exiting the TX LPI Mode 18.6.8.2. Gating Off the CSR Clock in the LPI Mode
18.6.8.2. Gating Off the CSR Clock in the LPI Mode x
18.6.8.2.1. Gating Off the CSR Clock in the RX LPI Mode 18.6.8.2.2. Gating Off the CSR Clock in the TX LPI Mode
18.6.9. Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output x
18.6.9.1. Generating a Single Pulse on PPS 18.6.9.2. Generating a Pulse Train on PPS 18.6.9.3. Generating an Interrupt without Affecting the PPS
19. USB 2.0 OTG Controller x
19.1. Features of the USB OTG Controller 19.2. USB OTG Controller Block Diagram and System Integration 19.3. USB 2.0 ULPI PHY Signal Description 19.4. Functional Description of the USB OTG Controller 19.5. USB OTG Controller Programming Model 19.6. USB 2.0 OTG Controller Address Map and Register Definitions
19.1. Features of the USB OTG Controller x
19.1.1. Supported PHYS
19.4. Functional Description of the USB OTG Controller x
19.4.1. USB OTG Controller Block Description 19.4.2. Local Memory Buffer 19.4.3. Clocks 19.4.4. Resets 19.4.5. Interrupts
19.4.1. USB OTG Controller Block Description x
19.4.1.1. Master Interface 19.4.1.2. Slave Interface 19.4.1.3. Application Interface Unit 19.4.1.4. Packet FIFO Controller 19.4.1.5. SPRAM 19.4.1.6. MAC 19.4.1.7. Wakeup and Power Control 19.4.1.8. PHY Interface Unit 19.4.1.9. DMA
19.4.1.2. Slave Interface x
19.4.1.2.1. Slave Interface CSR Unit
19.4.1.6. MAC x
19.4.1.6.1. USB Transactions 19.4.1.6.2. Host Protocol 19.4.1.6.3. Device Protocol 19.4.1.6.4. OTG Protocol
19.4.3. Clocks x
19.4.3.1. Clock Gating
19.4.4. Resets x
19.4.4.1. Reset Requirements 19.4.4.2. Hardware Reset 19.4.4.3. Software Reset 19.4.4.4. Taking the USB 2.0 OTG Controller Out of Reset
19.5. USB OTG Controller Programming Model x
19.5.1. Enabling ECC 19.5.2. Enabling SPRAM ECCs 19.5.3. Host Operation 19.5.4. Device Operation
19.5.3. Host Operation x
19.5.3.1. Host Initialization 19.5.3.2. Host Transaction
19.5.4. Device Operation x
19.5.4.1. Device Initialization 19.5.4.2. Device Transaction
19.5.4.2. Device Transaction x
19.5.4.2.1. IN Transactions 19.5.4.2.2. OUT Transactions 19.5.4.2.3. Control Transfers
20. SPI Controller x
20.1. Features of the SPI Controller 20.2. SPI Block Diagram and System Integration 20.3. SPI Controller Signal Description 20.4. Functional Description of the SPI Controller 20.5. SPI Programming Model 20.6. SPI Controller Address Map and Register Definitions
20.2. SPI Block Diagram and System Integration x
20.2.1. SPI Block Diagram
20.3. SPI Controller Signal Description x
20.3.1. Interface to HPS I/O 20.3.2. FPGA Routing
20.4. Functional Description of the SPI Controller x
20.4.1. Protocol Details and Standards Compliance 20.4.2. SPI Controller Overview 20.4.3. Transfer Modes 20.4.4. SPI Master 20.4.5. SPI Slave 20.4.6. Partner Connection Interfaces 20.4.7. DMA Controller Interface 20.4.8. Slave Interface 20.4.9. Clocks and Resets
20.4.2. SPI Controller Overview x
20.4.2.1. Serial Bit-Rate Clocks 20.4.2.2. Transmit and Receive FIFO Buffers 20.4.2.3. SPI Interrupts
20.4.2.1. Serial Bit-Rate Clocks x
20.4.2.1.1. SPI Master Bit-Rate Clock 20.4.2.1.2. SPI Slave Bit-Rate Clock
20.4.3. Transfer Modes x
20.4.3.1. Transmit and Receive 20.4.3.2. Transmit Only 20.4.3.3. Receive Only 20.4.3.4. EEPROM Read
20.4.4. SPI Master x
20.4.4.1. RXD Sample Delay 20.4.4.2. Data Transfers 20.4.4.3. Master SPI and SSP Serial Transfers 20.4.4.4. Master Microwire Serial Transfers
20.4.5. SPI Slave x
20.4.5.1. Slave SPI and SSP Serial Transfers  20.4.5.2. Serial Transfers 20.4.5.3. Glue Logic for Master Port ss_in_n
20.4.6. Partner Connection Interfaces x
20.4.6.1. Motorola SPI Protocol 20.4.6.2. Texas Instruments Synchronous Serial Protocol (SSP) 20.4.6.3. National Semiconductor Microwire Protocol
20.4.8. Slave Interface x
20.4.8.1. Control and Status Register Access 20.4.8.2. Data Register Access
20.4.9. Clocks and Resets x
20.4.9.1. Clock Gating 20.4.9.2. Taking the SPI Controller Out of Reset
20.5. SPI Programming Model x
20.5.1. Master SPI and SSP Serial Transfers 20.5.2. Master Microwire Serial Transfers 20.5.3. Slave SPI and SSP Serial Transfers 20.5.4. Slave Microwire Serial Transfers 20.5.5. Software Control for Slave Selection 20.5.6. DMA Controller Operation
20.5.5. Software Control for Slave Selection x
20.5.5.1. Example: Slave Selection Software Flow for SPI Master 20.5.5.2. Example: Slave Selection Software Flow for SPI Slave
20.5.6. DMA Controller Operation x
20.5.6.1. Transmit FIFO Buffer Underflow 20.5.6.2. Transmit FIFO Watermark 20.5.6.3. Transmit FIFO Buffer Overflow 20.5.6.4. Receive FIFO Buffer Overflow 20.5.6.5. Choosing Receive Watermark Level 20.5.6.6. Receive FIFO Buffer Underflow
20.5.6.2. Transmit FIFO Watermark x
20.5.6.2.1. Example 1: Transmit FIFO Watermark Level = 64 20.5.6.2.2. Example 2: Transmit FIFO Watermark Level = 192
21. I2C Controller x
21.1. Features of the I2C Controller 21.2. I2C Controller Block Diagram and System Integration 21.3. I2C Controller Signal Description 21.4. Functional Description of the I2C Controller 21.5. I2C Controller Programming Model 21.6. I 2 C Controller Address Map and Register Definitions
21.4. Functional Description of the I2C Controller x
21.4.1. Feature Usage 21.4.2. Behavior 21.4.3. Protocol Details 21.4.4. Multiple Master Arbitration 21.4.5. Clock Frequency Configuration 21.4.6. SDA Hold Time 21.4.7. DMA Controller Interface 21.4.8. Clocks 21.4.9. Resets
21.4.2. Behavior x
21.4.2.1. START and STOP Generation 21.4.2.2. Combined Formats
21.4.3. Protocol Details x
21.4.3.1. START and STOP Conditions 21.4.3.2. Addressing Slave Protocol 21.4.3.3. Transmitting and Receiving Protocol 21.4.3.4. START BYTE Transfer Protocol
21.4.3.2. Addressing Slave Protocol x
21.4.3.2.1. 7-Bit Address Format 21.4.3.2.2. 10-Bit Address Format
21.4.3.3. Transmitting and Receiving Protocol x
21.4.3.3.1. Master-Transmitter and Slave-Receiver 21.4.3.3.2. Master-Receiver and Slave-Transmitter
21.4.4. Multiple Master Arbitration x
21.4.4.1. Clock Synchronization
21.4.5. Clock Frequency Configuration x
21.4.5.1. Minimum High and Low Counts
21.4.5.1. Minimum High and Low Counts x
21.4.5.1.1. Calculating High and Low Counts
21.4.9. Resets x
21.4.9.1. Taking the I2C Controller Out of Reset
21.5. I2C Controller Programming Model x
21.5.1. Slave Mode Operation 21.5.2. Master Mode Operation 21.5.3. Disabling the I2C Controller 21.5.4. Abort Transfer 21.5.5. DMA Controller Operation
21.5.1. Slave Mode Operation x
21.5.1.1. Initial Configuration 21.5.1.2. Slave-Transmitter Operation for a Single Byte 21.5.1.3. Slave-Receiver Operation for a Single Byte 21.5.1.4. Slave-Transfer Operation for Bulk Transfers 21.5.1.5. Slave Programming Model
21.5.2. Master Mode Operation x
21.5.2.1. Initial Configuration 21.5.2.2. Dynamic IC_TAR or IC_10BITADDR_MASTER Update 21.5.2.3. Master Transmit and Master Receive 21.5.2.4. Master Programming Model
21.5.5. DMA Controller Operation x
21.5.5.1. Transmit FIFO Underflow 21.5.5.2. Transmit Watermark Level 21.5.5.3. Transmit FIFO Overflow 21.5.5.4. Receive FIFO Overflow 21.5.5.5. Receive Watermark Level 21.5.5.6. Receive FIFO Underflow
22. UART Controller x
22.1. UART Controller Features 22.2. UART Controller Block Diagram and System Integration 22.3. UART Controller Signal Description 22.4. Functional Description of the UART Controller 22.5. DMA Controller Operation 22.6. UART Controller Address Map and Register Definitions
22.3. UART Controller Signal Description x
22.3.1. HPS I/O Pins 22.3.2. FPGA Routing
22.4. Functional Description of the UART Controller x
22.4.1. FIFO Buffer Support 22.4.2. UART(RS232) Serial Protocol 22.4.3. Automatic Flow Control 22.4.4. Clocks 22.4.5. Resets 22.4.6. Interrupts
22.4.3. Automatic Flow Control x
22.4.3.1. RTC Flow Control Trigger 22.4.3.2. Automatic RTS mode 22.4.3.3. Automatic CTS mode
22.4.5. Resets x
22.4.5.1. Taking the UART Controller Out of Reset
22.4.6. Interrupts x
22.4.6.1. Programmable THRE Interrupt
22.5. DMA Controller Operation x
22.5.1. Transmit FIFO Underflow 22.5.2. Transmit Watermark Level 22.5.3. Transmit FIFO Overflow 22.5.4. Receive FIFO Overflow 22.5.5. Receive Watermark Level 22.5.6. Receive FIFO Underflow
22.5.2. Transmit Watermark Level x
22.5.2.1. IIR_FCR.TET = 1 22.5.2.2. IIR_FCR.TET = 3
23. General-Purpose I/O Interface x
23.1. Features of the GPIO Interface 23.2. GPIO Interface Block Diagram and System Integration 23.3. Functional Description of the GPIO Interface 23.4. GPIO Interface Programming Model 23.5. General-Purpose I/O Interface Address Map and Register Definitions
23.3. Functional Description of the GPIO Interface x
23.3.1. Debounce Operation 23.3.2. Pin Directions 23.3.3. Taking the GPIO Interface Out of Reset
24. Timer x
24.1. Features of the Timer 24.2. Timer Block Diagram and System Integration 24.3. Functional Description of the Timer 24.4. Timer Programming Model 24.5. Timer Address Map and Register Definitions
24.3. Functional Description of the Timer x
24.3.1. Clocks 24.3.2. Resets 24.3.3. Interrupts
24.4. Timer Programming Model x
24.4.1. Initialization 24.4.2. Enabling the Timer 24.4.3. Disabling the Timer 24.4.4. Loading the Timer Countdown Value 24.4.5. Servicing Interrupts
24.4.5. Servicing Interrupts x
24.4.5.1. Clearing the Interrupt 24.4.5.2. Checking the Interrupt Status 24.4.5.3. Masking the Interrupt
25. Watchdog Timer x
25.1. Features of the Watchdog Timer 25.2. Watchdog Timer Block Diagram and System Integration 25.3. Functional Description of the Watchdog Timer 25.4. Watchdog Timer Programming Model 25.5. Watchdog Timer Address Map and Register Definitions
25.3. Functional Description of the Watchdog Timer x
25.3.1. Watchdog Timer Counter 25.3.2. Watchdog Timer Pause Mode 25.3.3. Watchdog Timer Clocks 25.3.4. Watchdog Timer Resets
25.3.4. Watchdog Timer Resets x
25.3.4.1. Taking the Watchdog Timer Out of Reset
25.4. Watchdog Timer Programming Model x
25.4.1. Setting the Timeout Period Values 25.4.2. Selecting the Output Response Mode 25.4.3. Enabling and Initially Starting a Watchdog Timer 25.4.4. Reloading a Watchdog Counter 25.4.5. Pausing a Watchdog Timer 25.4.6. Disabling and Stopping a Watchdog Timer 25.4.7. Watchdog Timer State Machine
26. Hard Processor System I/O Pin Multiplexing x
26.1. Features of the HPS I/O Block 26.2. HPS I/O Block Diagram and System Integration 26.3. Functional Description of the HPS I/O 26.4. Test Considerations 26.5. I/O Pin MUX Address Map and Register Definitions for Arria 10
26.3. Functional Description of the HPS I/O x
26.3.1. Dedicated I/O Pins 26.3.2. Shared I/O Pins 26.3.3. FPGA Access 26.3.4. Control Registers 26.3.5. Configuring HPS I/O Multiplexing
26.3.1. Dedicated I/O Pins x
26.3.1.1. Warm Reset Pin 26.3.1.2. Boot Pins
26.3.4. Control Registers x
26.3.4.1. Dedicated Pin MUX Registers 26.3.4.2. Dedicated Configuration Registers 26.3.4.3. Shared Pin MUX Registers 26.3.4.4. FPGA Access MUX Registers
26.3.5. Configuring HPS I/O Multiplexing x
26.3.5.1. Configuring Multiplexing at System Generation 26.3.5.2. Configuring Multiplexing at Boot Time
27. Introduction to the HPS Component x
27.1. MPU Subsystem 27.2. Arm* CoreSight* Debug Components 27.3. Interconnect 27.4. HPS-to-FPGA Interfaces 27.5. Memory Controllers 27.6. Support Peripherals 27.7. Interface Peripherals 27.8. On-Chip Memories
27.5. Memory Controllers x
27.5.1. HPS SDRAM Controller
27.5.1. HPS SDRAM Controller x
27.5.1.1. HMC and HPS Connectivity 27.5.1.2. Clocks 27.5.1.3. Resets
28. Instantiating the HPS Component x
28.1. Using the HPS Parameter Editor 28.2. FPGA Interfaces 28.3. Configuring HPS Clocks and Resets 28.4. Configuring Peripheral Pin Multiplexing 28.5. Configuring the External Memory Interface 28.6. Using the Address Span Extender Component 28.7. Generating and Compiling the HPS Component
28.2. FPGA Interfaces x
28.2.1. General Interfaces 28.2.2. FPGA-to-HPS SDRAM Interface 28.2.3. DMA Peripheral Request 28.2.4. Security Manager 28.2.5. Interrupts 28.2.6. AXI Bridges
28.3. Configuring HPS Clocks and Resets x
28.3.1. Alternate Clock Source from FPGA 28.3.2. User Clocks 28.3.3. Reset Interfaces 28.3.4. Peripheral FPGA Clocks
28.3.2. User Clocks x
28.3.2.1. User Clock Parameters 28.3.2.2. Clock Frequency Usage
28.4. Configuring Peripheral Pin Multiplexing x
28.4.1. Configuring Peripherals 28.4.2. Connecting Unassigned Pins to GPIO 28.4.3. Peripheral Signals Routed to FPGA
28.4.1. Configuring Peripherals x
28.4.1.1. Boot Source
29. HPS Component Interfaces x
29.1. Memory-Mapped Interfaces 29.2. Clocks 29.3. Resets 29.4. Debug and Trace Interfaces 29.5. Peripheral Signal Interfaces 29.6. Other Interfaces
29.1. Memory-Mapped Interfaces x
29.1.1. FPGA-to-HPS Bridge 29.1.2. HPS-to-FPGA and Lightweight HPS-to-FPGA Bridges 29.1.3. FPGA-to-HPS SDRAM Interface 29.1.4. EMIF Conduit
29.2. Clocks x
29.2.1. Alternative Clock Inputs to HPS PLLs 29.2.2. User Clocks 29.2.3. AXI Bridge FPGA Interface Clocks 29.2.4. SDRAM Clocks 29.2.5. Peripheral FPGA Clocks
29.3. Resets x
29.3.1. HPS-to-FPGA Reset Interfaces 29.3.2. HPS External Reset Request 29.3.3. Peripheral Reset Interfaces
29.4. Debug and Trace Interfaces x
29.4.1. FPGA System Trace Macrocell Events Interface 29.4.2. FPGA Cross Trigger Interface 29.4.3. Debug APB* Interface
29.5. Peripheral Signal Interfaces x
29.5.1. Platform Designer (Standard) Peripheral Port Interface Mapping 29.5.2. DMA Controller Interface
29.5.1. Platform Designer (Standard) Peripheral Port Interface Mapping x
29.5.1.1. NAND Flash Controller Interface 29.5.1.2. SD/MMC Controller Interface 29.5.1.3. Quad SPI Flash Controller Interface 29.5.1.4. Ethernet Media Access Controller Interface 29.5.1.5. USB 2.0 OTG Controller Interface 29.5.1.6. SPI Controller Interface 29.5.1.7. I2C Controller Interface 29.5.1.8. UART Interface
29.6. Other Interfaces x
29.6.1. MPU Standby and Event Interfaces 29.6.2. General Purpose Signals 29.6.3. FPGA-to-HPS Interrupts 29.6.4. Boot from FPGA Interface 29.6.5. Security Manager
30. Simulating the HPS Component x
30.1. Simulation Flows 30.2. Clock and Reset Interfaces 30.3. FPGA-to-HPS AXI Slave Interface 30.4. HPS-to-FPGA AXI Master Interface 30.5. Lightweight HPS-to-FPGA AXI Master Interface 30.6. HPS-to-FPGA MPU Event Interface 30.7. Interrupts Interface 30.8. HPS-to-FPGA Debug APB* Interface 30.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface 30.10. HPS-to-FPGA Cross-Trigger Interface 30.11. FPGA-to-HPS DMA Handshake Interface 30.12. Boot from FPGA Interface 30.13. Security Manager Anti-Tamper Signals Interface 30.14. EMIF Conduit 30.15. Pin MUX and Peripherals
30.1. Simulation Flows x
30.1.1. Setting Up the HPS Component for Simulation 30.1.2. Generating the HPS Simulation Model in Platform Designer (Standard) 30.1.3. Running the Simulations
30.1.1. Setting Up the HPS Component for Simulation x
30.1.1.1. HPS Conduit Interfaces Connecting to the FPGA
30.1.1.1. HPS Conduit Interfaces Connecting to the FPGA x
30.1.1.1.1. Setting Up the HPS Component for Simulation
30.1.3. Running the Simulations x
30.1.3.1. Running HPS RTL Simulation 30.1.3.2. Running HPS Post-Fit Simulation
30.1.3.2. Running HPS Post-Fit Simulation x
30.1.3.2.1. Post-Fit Simulation Files 30.1.3.2.2. BFM API Hierarchy Format
30.2. Clock and Reset Interfaces x
30.2.1. Clock Interface 30.2.2. Reset Interface
30.15. Pin MUX and Peripherals x
30.15.1. HPS Conduit Interfaces Connecting to the HPS I/O 30.15.2. HPS Conduit Interfaces Connecting to the FPGA
A. Booting and Configuration x
A.1. Boot Overview A.2. FPGA Configuration Overview A.3. Booting and Configuration Options A.4. Boot Definitions A.5. Boot ROM Flow A.6. Second-Stage Boot Flow A.7. FPGA Configuration A.8. FPGA Reconfiguration
A.4. Boot Definitions x
A.4.1. Reset A.4.2. Boot ROM A.4.3. Boot Select A.4.4. Flash Memory Devices for Booting A.4.5. Clock Select A.4.6. I/O Configuration A.4.7. L4 Watchdog 0 Timer A.4.8. Second-Stage Boot Loader A.4.9. Secure Boot
A.4.3. Boot Select x
A.4.3.1. Boot Source I/O Pins A.4.3.2. Boot Fuses
A.4.4. Flash Memory Devices for Booting x
A.4.4.1. SD/MMC Flash Devices A.4.4.2. NAND Flash Devices A.4.4.3. Quad SPI Flash Devices
A.4.4.1. SD/MMC Flash Devices x
A.4.4.1.1. Default Settings of the SD/MMC Controller A.4.4.1.2. CSEL Settings for the SD/MMC Controller
A.4.4.2. NAND Flash Devices x
A.4.4.2.1. NAND Flash Driver Features Supported in the Boot ROM Code A.4.4.2.2. CSEL Settings for the NAND Controller
A.4.4.3. Quad SPI Flash Devices x
A.4.4.3.1. Quad SPI Controller Default Settings A.4.4.3.2. Quad SPI Flash Delay Configuration A.4.4.3.3. Quad SPI Controller CSEL Settings
A.4.6. I/O Configuration x
A.4.6.1. I/O State
A.6. Second-Stage Boot Flow x
A.6.1. Typical Boot Flow (Non-Secure) A.6.2. Secure Boot Flow A.6.3. HPS State on Entry to the Second-Stage Boot Loader A.6.4. Loading the Second-Stage Boot Loader Image
A.7. FPGA Configuration x
A.7.1. Full FPGA Configuration Flow Through HPS A.7.2. Early I/O Release FPGA Configuration Flow Through HPS A.7.3. Arria 10 SoC FPGA Configuration Sequence Through FPGA Manager
A.7.2. Early I/O Release FPGA Configuration Flow Through HPS x
A.7.2.1. Handling an FPGA Configuration Failure after Early I/O Release
A.8. FPGA Reconfiguration x
A.8.1. Full FPGA Reconfiguration A.8.2. Arria 10 SoC FPGA Partial Reconfiguration Sequence Through FPGA Manager
1. Intel® Arria® 10 Hard Processor System Technical Reference Manual Revision History
2. Introduction to the Hard Processor System
3. Clock Manager
4. Reset Manager
5. FPGA Manager
6. System Manager
7. SoC Security
8. System Interconnect
9. HPS-FPGA Bridges
10. Cortex*-A9 Microprocessor Unit Subsystem
11. CoreSight* Debug and Trace
12. Error Checking and Correction Controller
13. On-Chip Memory
14. NAND Flash Controller
15. SD/MMC Controller
16. Quad SPI Flash Controller
17. DMA Controller
18. Ethernet Media Access Controller
19. USB 2.0 OTG Controller
20. SPI Controller
21. I2C Controller
22. UART Controller
23. General-Purpose I/O Interface
24. Timer
25. Watchdog Timer
26. Hard Processor System I/O Pin Multiplexing
27. Introduction to the HPS Component
28. Instantiating the HPS Component
29. HPS Component Interfaces
30. Simulating the HPS Component
A. Booting and Configuration

14.5. NAND Flash Controller Programming Model

This section describes how the NAND flash controller is to be programmed by software running on the microprocessor unit (MPU).
Note: If you write a configuration register and follow it up with a data operation that is dependent on the value of this configuration register, Intel recommends that you read the value of the register before performing the data operation. This read operation ensures that the posted write of the register is completed and takes effect before the data operation is issued to the NAND flash controller.

Basic Flash Programming

This section describes the steps that must be taken by the software to access and control the NAND flash controller.

NAND Flash Controller Optimization Sequence

The software must configure the flash device for interrupt or polling mode, using the bank0 bit of the rb_pin_enabled register in the config group. If the device is in polling mode, the software must also program the additional registers, to select the times and frequencies of the polling. Program the following registers in the config group:
  • Set the rb_pin_enabled register to the desired mode of operation for each flash device.
  • For polling mode, set the load_wait_cnt register to the appropriate value depending on the speed of operation of the NAND flash controller, and the desired wait value.
  • For polling mode, set the program_wait_cnt register to the appropriate value by software depending on the speed of operation of the NAND flash controller, and the desired wait value.
  • For polling mode, set the erase_wait_cnt register to the appropriate value by software depending on the speed of operation of the NAND flash controller, and the desired wait value.
  • For polling mode, set the int_mon_cyccnt register to the appropriate value by software depending on the speed of operation of the NAND flash controller, and the desired wait value.

At any time, the software can change any flash device from interrupt mode to polling mode or vice‑versa, using the bank0 bit of the rb_pin_enabled register.

The software must ensure that the particular flash device does not have any outstanding transactions before changing the mode of operation for that particular flash device.

Device Initialization Sequence

At initialization, the host software must program the following registers in the config group:
  • Set the devices_connected register to 1.
  • Set the device_width register to 8.
  • Set the device_main_area_size register to the appropriate value.
  • Set the device_spare_area_size register to the appropriate value.
  • Set the pages_per_block register according to the parameters of the flash device.
  • Set the number_of_planes register according to the parameters of the flash device.
  • If the device allows two ROW address cycles, the flag bit of the two_row_addr_cycles register must be set to 1. The host program can ensure this condition either of the following ways:
    • Set the flag bit of the bootstrap_two_row_addr_cycles register to 1 prior to the NAND flash controller’s reset initialization sequence, causing the flash controller to initialize the bit automatically.
    • Set the flag bit of the two_row_addr_cycles register directly to 1.
  • Clear the chip_enable_dont_care register in the config group to 0.

The NAND flash controller can identify the flash device features, allowing you to initialize the flash controller registers to interface correctly with the device, as described in Discovery and Initialization.

However, a few NAND devices do not follow any universally accepted identification protocol. If connected to such a device, the NAND flash controller cannot identify it correctly. If you are using such a device, your software must use other means to ensure that the initialization registers are set up correctly.

Device Operation Control

This section provides a list of registers that you need to program while choosing to use multi‑plane or cache operations on the device. If the device does not support multi‑plane operations or cache operations, then these registers can be left at their power‑on reset values with no impact on the functionality of the NAND flash controller. Even if the device supports these sequences, the software does not need to use them. Software can leave these registers at their power‑on reset values.

Program the following registers in the config group to achieve the best performance from a given device:

  • Set flag bit in the multiplane_operation register in the config group to 1 if the device supports multi‑plane operations to access the data on the flash device connected to the NAND flash controller. If the flash controller is set up for multi‑plane operations, the number of pages to be accessed is always a multiple of the number of planes in the device.
  • If the NAND flash controller is configured for multi‑plane operation, and if the device has support for multi‑plane read command sequence, set the multiplane_read_enable register in the config group.
  • If the device implements multiplane address restrictions, set the flag bit in the multiplane_addr_restrict register to 1.
  • Initialize the die_mask and first_block_of_next_plane registers as per device requirements.
  • If the device supports cache command sequences, enable the cache_write_enable and cache_read_enable registers in the config group.
  • Clear the flag bit of the copyback_disable register in the config group to 0 if the device does not support the copyback command sequences. The register defaults to enabled state.
  • The read_mode, write_mode and copyback_mode registers, in the config group, currently need not be written by software, because the NAND flash controller is capable of using the correct sequences based on a combination of some multi‑plane or cache‑related settings of the NAND flash controller and the manufacturer ID. If at some future time these settings change, program the registers to accommodate the change.

ECC Enabling

Before you start any data operation on the flash device, you must decide whether you want the ECC enabled or disabled.

To prevent spurious ECC errors, software must use the memory initialization block in the ECC controller to clear the entire memory data and initialize the ECC bits. The initialization block clears the memory data. Initializing the memory with the initialization block is independent of enabling the ECC.

If the ECC needs enabling, set up the appropriate correction level depending on the page size and the spare area available on the device.

Set the flag bit in the ecc_enable register in the config group to 1 to enable ECC. If enabled, the following registers in the config group must be programmed accordingly, else they can be ignored:

  • Initialize the ecc_correction register to the appropriate correction level.
  • Program the spare_area_skip_bytes and spare_area_marker registers in the config group if the software needs to preserve the bad block marker.

NAND Flash Controller Performance Registers

These registers specify the size of the bursts on the device interface, which maximizes the overall performance on the NAND flash controller.

Initialize the flash_burst_length register in the dma group to a value which maximizes the performance of the device interface by minimizing the number of bursts required to transfer a page.

Interrupt and DMA Enabling

Prior to initiating any data operation on the NAND flash controller, the software must set appropriate interrupt status register bits. If the software uses the DMA logic in the flash controller, then the appropriate DMA enable and interrupts bits in the register space must be set.
  1. Set the flag bit in the global_int_enable register in the config group to 1, to enable global interrupt.
  2. Set the relevant bits of the intr_en0 register in the status group to 1 before initiating any operations if the flash controller is in interrupt mode. Intel recommends that the software reads back this register to ensure clearing an interrupt status. This recommendation applies also to an interrupt service routine.
  3. Enable DMA if your application needs DMA mode. Enable DMA by setting the flag bit of the dma_enable register in the dma group. Intel recommends that the software reads back this register to ensure that the mode change is accepted before sending a DMA command to the flash controller.
  4. If the DMA is enabled, then set up the appropriate bits of the dma_intr_en register in the dma group.

Order of Interrupt Status Bits Assertion

The following interrupt status bits, in the intr_status0 register in the status group, are listed in the order of interrupt bit setting:
  1. time_out—All other interrupt bits are set to 0 when the watchdog time_out bit is asserted.
  2. dma_cmd_comp—This bit signifies the completion of data transfer sequence.32
  3. pipe_cpybck_cmd_comp—This bit is asserted when a copyback command or the last page of a pipeline command completes.
  4. locked_blk—This bit is asserted when a program (or erase) is performed on a locked block.
  5. INT_act—No relationship with other interrupt status bits. Indicates a transition from 0 to 1 on the ready_busy pin value for that flash device.
  6. rst_comp—No relationship with other interrupt status bits. Occurs after a reset command has completed.
  7. For an erase command:
    1. erase_fail (if failure)
    2. erase_comp
  8. For a program command:
    1. locked_blk (if performed on a locked block)
    2. pipe_cmd_err (if the pipeline sequence is broken by a MAP01 command)
    3. page_xfer_inc (at the end of each page data transfer)
    4. program_fail (if failure)
    5. pipe_cpybck_cmd_comp
    6. program_comp
    7. dma_cmd_comp (If DMA enabled)
  9. For a read command:
    1. pipe_cmd_err (if the pipeline sequence is broken by a MAP01 command)
    2. page_xfer_inc (at the end of each page data transfer)
    3. pipe_cpybck_cmd_comp
    4. load_comp
    5. ecc_uncor_error (if failure)
    6. dma_cmd_comp (If DMA enabled)

Timing Registers

You must optimize the following registers for your flash device’s speed grade and clock frequency. The NAND flash controller operates correctly with the power‑on reset values. However, functioning with power‑on reset values is a non‑optimal mode that provides loose timing (large margins to the signals).

Set the following registers in the config group to optimize the NAND flash controller for the speed grade of the connected device and frequency of operation of the flash controller:

  • twhr2_and_we_2_re
  • tcwaw_and_addr_2_data
  • re_2_we
  • acc_clks
  • rdwr_en_lo_cnt
  • rdwr_en_hi_cnt
  • max_rd_delay
  • cs_setup_cnt
  • re_2_re
Note:

In the case of the reading process mechanism, the NAND controller operates in two work modes: Boot mode and Performance mode.

After reset, the controller starts in Boot mode. In this mode, the data sampling doesn't depend on the default value of acc_clks or max_rd_delay registers but the correct sampling is warranted (with low performance) using the default values of the other registers listed above. The NAND controller remains in Boot mode as long as the value of acc_clks register remains in 0 (default value).

Once the acc_clks register takes a different value, the controller switches to Performance mode. In Performance mode, the data sampling on read operations now follows the functionality described in the acc_clks and max_rd_delay registers. The NAND controller remains in Performance mode until a reset occurs; for example, returning a value of 0 in acc_clks register doesn't make the controller to transit back to Boot mode again.

Registers to Ignore

You do not need to initialize the following registers in the config group:
  • The transfer_spare_reg register—Data transfer mode can be initialized using MAP10 commands.
  • The write_protect register—Does not need initializing unless you are testing the write protection feature.

Flash-Related Special Function Operations

This section describes all the special functions that can be performed on the flash memory.

The functions are defined by MAP10 commands as described in Command Mapping.

Erase Operations

Before data can be written to flash, an erase cycle must occur. The NAND flash memory controller supports single block and multi‑plane erases.

The controller decodes the block address from the indirect addressing shown in "MAP10 Command Format".

Single Block Erase

A single command is needed to complete a single‑block erase, as follows:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the desired erase block.
  2. Write 0x01 to the Data register.

For a single block erase, the register multiplane_operation in the config group must be reset.

After the device completes the erase operation, the controller generates an erase_comp interrupt. If the erase operation fails, the erase_fail interrupt is issued. The failing block's address is updated in the err_block_addr0 register in the status group.

Multi-Plane Erase

For multi‑plane erases, the number_of_planes register in the config group holds the number of planes in the flash device, and the block address specified must be aligned to the number of planes in the device. The NAND flash controller consecutively erases each block of the memory, up to the number of planes available. Issue this command as follows:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the desired erase block.
  2. Write 0x01 to the Data register.

For multi‑plane erase, the register multiplane_operation in the config group must be set.

After the device completes erase operation on all planes, the NAND flash controller generates an erase_comp interrupt. If the erase operation fails on any of the blocks in a multi‑plane erase command, an erase_fail interrupt is issued. The failing block's address is updated in the err_block_addr0 register in the status group.

Lock Operations

The NAND flash controller supports the following features:
  • Flash locking—The NAND flash controller supports all flash locking operations.

    The flash device itself might have limited support for these functions. If the device does not support locking functions, the flash controller ignores these commands.

  • Lock‑tight—With the lock‑tight feature, the NAND flash controller can prevent lock status from being changed. After the memory is locked tight, the flash controller must be reset before any flash area can be locked or unlocked.

Unlocking a Span of Memory Blocks

To unlock several blocks of memory, perform the following steps:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the starting address of the area to unlock.
  2. Write 0x10 to the Data register.
  3. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the ending address of the area to unlock.
  4. Write 0x11 to the Data register.

When unlocking a range of blocks, the start block address must be less than the end block address. Otherwise, the NAND flash controller exhibits undetermined behavior.

Locking All Memory Blocks

To lock the entire memory:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to any memory address.
  2. Write 0x21 to the Data register.

Setting Lock-Tight on All Memory Blocks

After the lock‑tight is applied, unlocked areas cannot be locked, and locked areas cannot be unlocked. To lock‑tight the entire memory:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to any memory address.
  2. Write 0x31 to the Data register.

To disable the lock‑tight, reset the memory controller.

Transfer Mode Operations

You can configure the NAND flash controller in one of the following modes of data transfer:
  • Default area transfer mode
  • Spare area transfer mode
  • Main+spare area transfer mode

The NAND flash controller determines the default transfer mode from the setting of transfer_spare_reg register in the config group. Use MAP10 commands to dynamically change the transfer mode from the existing mode to the new mode. All subsequent commands are in the new mode of transfer. You must consider that transfer modes can be changed at logical data transfer boundaries. For example:

  • At the beginning or end of a page in case of single page read or write.
  • At the beginning or end of a complete multi‑page pipeline read or write command.

transfer_spare_reg and MAP10 Transfer Mode Commands

The following table lists the functionality of the MAP10 transfer mode commands, and their mappings to the transfer_spare_reg register in the config group.
Table 134.  transfer_spare_reg and MAP10 Transfer Mode Commands
transfer_spare_reg MAP10 Transfer Mode Commands Resulting NAND Flash Controller Mode

0

0x42

Main33

0

0x41

Spare

0

0x43

Main+spare

1

0x42

Main+spare33

1

0x41

Spare

1

0x43

Main+spare

Configure for Default Area Access

You only need to configure for default area access if the transfer mode was previously changed to spare area or main+spare area. To configure default area access:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to any block.
  2. Write 0x42 to the Data register.

The NAND flash controller determines the default area transfer mode from the setting of the transfer_spare_reg register in the config group. If it is set to 1, then the transfer mode becomes main+spare area, otherwise it is main area.

Configure for Spare Area Access

To access only the spare area of the flash device, use the MAP10 command to set up the NAND flash controller to read or write only the spare area on the device. After the flash controller is set up, use MAP01 read and write commands to access the spare area of the appropriate block and page addresses. To configure the NAND flash controller to access the spare area only, perform the following steps:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the target block.
  2. Write 0x41 to the Data register.

Configure for Main+Spare Area Access

To configure the NAND flash controller to access the main+spare area:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ ADDR field to the target block.
  2. Write 0x43 to the Data register.

Read-Modify-Write Operations

To read a specific page or modify a few words, bytes, or bits in a page, use the RMW operations. A read command copies the desired data from flash memory to a page buffer. You can then modify the information in the buffer using MAP00 buffer read and write commands and issue another command to write that information back to the memory.

The read‑modify‑write command operates on an entire page. This command is also useful for a copy type operation, where most of a page is saved to a new location. In this type of operation, the NAND flash controller reads the data, modifies a specified number of words in the page, and then writes the modified page to a new location.

Note: Because the data is modified within the page buffer of the flash device, the NAND flash controller ECC hardware is not used in RMW operations. Software must update the ECC during RMW operations.
Note: For a read‑modify‑write command to work with hardware ECC, the entire page must be read into system memory, modified, then written back to flash without relying on the RMW feature.

Read-Modify-Write Operation Flow

  1. Start the flow by reading a page from the memory:
    • Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the starting address of the desired block.
    • Write 0x60 to the Data register.
    This step makes the page available to you in the page buffer in the flash device.
  2. Provide the destination page address:
    • Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the destination address of the desired block.
    • Write 0x61 to the Data register.
    This step initiates the page program and provides the destination address to the device.
  3. Use the MAP00 page buffer read and write commands to modify the data in the page buffer.
  4. Write the page buffer data back to memory:
    • Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the same destination address.
    • Write 0x62 to the Data register.
    This step performs the write.

After the device completes the load operation, the NAND flash controller issues a load_comp interrupt. A program_comp interrupt is issued when the host issues the write command and the device completes the program operation.

If the page program operation (as a part of an RMW operation) results in a program failure in the device, program_fail interrupt is issued. The failing page's block and page address is updated in the err_block_addr0 and err_page_addr0 registers in the status group.

Copy-Back Operations

The NAND flash controller supports copy back operations. However, the flash device might have limited support for this function. If you attempt to perform a copy‑back operation on a device that does not support copy‑back, the NAND flash controller triggers an interrupt. An interrupt is also triggered if the source block is not specified before the destination block is specified, or if the destination block is not specified in the next command following a source block specification.

The NAND flash controller cannot do ECC validation in case of copy‑back commands. The flash controller copies the ECC data, but does not check it during the copy operation.

Note: Intel recommends that you use copy‑back only if the ECC implemented in the flash controller is strong enough so that the next access can correct accumulated errors.

The 8‑bit value <PP> specifies the number of pages for copy‑back. With this feature, the NAND flash controller can copy multiple consecutive pages with a single command. When you issue a copy‑back command, the flash controller performs the operation in the background. The flash controller puts other commands on hold until the current copy‑back completes.

For a multi‑plane device, if the flag bit in the multiplane_operation register in the config group is set to 1, multi‑plane copy‑back is available as an option. In this case, the block address specified must be plane‑aligned and the value <PP> must specify the total number of pages to copy as a multiple of the number of planes. The block address continues incrementing, keeping the page address fixed, for the total number of planes in the device before incrementing the page address.

A pipe_cpyback_cmd_comp interrupt is generated when the flash controller has completed copy‑back operation of all <PP> pages. If any page program operation (as a part of copy back operation) results in a program failure in the device, the program_fail interrupt is issued. The failing page's block and page address is updated in the err_block_addr0 and err_page_addr0 registers in the status group.

Copying a Memory Area (Single Plane)

To copy <PP> pages from one memory location to another:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the starting address of the area to be copied.
  2. Write 0x1000 to the Data register.
  3. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the starting address of the new area to be written.
  4. Write 0x11<PP> to the Data register, where <PP> is the number of pages to copy.

Copying a Memory Area (Multi-Plane)

To copy <PP> pages from one memory location to another:
  1. Set the flag bit of the multiplane_operation register in the config group to 1.
  2. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the starting address of the area to be copied. The address must be plane‑aligned.
  3. Write 0x1000 to the Data register.
  4. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the starting address of the new area to be written. This address must also be plane‑aligned.
  5. Write 0x11<PP> to the Data register, where <PP> is the number of pages to copy.

The parameter <PP> must be a multiple of the number of planes in the device.

Pipeline Read-Ahead and Write-Ahead Operations

The NAND flash controller supports pipeline read‑ahead and write‑ahead operations. However, the flash device might have limited support for this function. If the device does not support pipeline read‑ahead or write‑ahead, the flash controller processes these commands as standard reads or writes.

The NAND flash controller can handle at the most four outstanding pipeline commands, queued up in the order in which the flash controller received the commands. The flash controller operates on the pipeline command at the head of the queue until all the pages corresponding to the pipeline command are executed. The flash controller then pops the pipeline command at the head of the queue and proceeds to work on the next pipeline command in the queue.

Pipeline Read-Ahead Function

The pipeline read‑ahead function allows for a continuous reading of the flash memory. On receiving a pipeline read command, the flash controller immediately issues a load command to the device. While data is read out with MAP01 commands in a consecutive or multi‑plane address pattern, the flash controller maintains additional cache or multi‑plane read command sequencing for continuous streaming of data from the flash device.

Pipeline read‑ahead commands can read data from the queue in this interleaved fashion. The parameter <PP> denotes the total number of pages in multiples of the number of planes available, and the block address must be plane‑aligned, which keeps the page address constant while incrementing the block address for each page‑size chunk of data. After reading from every plane, the NAND flash controller increments the page address and resets the block address to the initial address. You can also use pipeline write‑ahead commands in multi‑plane mode. The write operation works similarly to the read operation, holding the page address constant while incrementing the block address until all planes are written.

Note: The same four‑entry queue is used to queue the address and page count for pipeline read‑ahead and write‑ahead commands. This commonality requires that you use MAP01 commands to read out all pages for a pipeline read‑ahead command before the next pipeline command can be processed. Similarly, you must write to all pages pertaining to pipeline write‑ahead command before the next pipeline command can be processed.

Because the value of the flag bit of the multiplane_operation register in the config group determines pipeline read‑ahead or write‑ahead behavior, it can only be changed when the pipeline registers are empty.

When the host issues a pipeline read‑ahead command, and the flash controller is idle, the load operation occurs immediately.

Note: The read‑ahead command does not return the data to the host, and the write‑ahead command does not write data to the flash address. The NAND flash controller loads the read data. The read data is returned to the host only when the host issues MAP01 commands to read the data. Similarly, the flash controller loads the write data, and writes it to the flash only when the host issues MAP01 commands to write the data.
Set Up a Single Area for Pipeline Read-Ahead
To set up an area for pipeline read‑ahead, perform the following steps:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the starting address of the block to pre‑read.
  2. Write 0x20<PP> to the Data register, where the 0 sets this command as a read‑ahead and <PP> is the number of pages to pre‑read. The pages must not cross a block boundary. If a block boundary is crossed, the NAND flash controller generates an unsupported command (unsup_cmd) interrupt and drops the command.

The read‑ahead command is a hint to the flash device to start loading the next page in the page buffer as soon as the previous page buffer operation has completed. After you set up the read‑ahead, use a MAP01 command to actually read the data. In the MAP01 command, specify the same starting address as in the read‑ahead.

If the read command received following a pipeline read‑ahead request is not to a pre‑read page, then an interrupt bit is set to 1 and the pipeline read‑ahead or write‑ahead registers are cleared. You must issue a new pipeline read‑ahead request to re‑load the same data. You must use MAP01 commands to read all of the data that is pre‑read before the NAND flash controller returns to the idle state.

Pipeline Write-Ahead Function

The pipeline write‑ahead function allows for a continuous writing of the flash memory. While data is written with MAP01 commands in a consecutive or multi‑plane address pattern, the NAND flash controller maintains cache or multi‑plane command sequences for continuous streaming of data into the flash device.

For pipeline write commands, if any page program results in a failure in the device, a program_fail interrupt is issued. The failing page's block and page addresses are updated in the err_block_addr0 and err_page_addr0 registers in the status group.

Set Up a Single Area for Pipeline Write-Ahead
To set up an area for pipeline write‑ahead:
  1. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the starting address of the block to pre‑write.
  2. Write 0x21<PP> to the Data register, where the value 1 sets this command as a write‑ahead and <PP> is the number of pages to pre‑write. The pages must not cross a block boundary. If a block boundary is crossed, the NAND flash controller generates an unsupported command (unsup_cmd) interrupt and drops the command.

After you set up the write‑ahead, use a MAP01 command to write the data. In the MAP01 command, specify the same starting address as in the write‑ahead.

If the write command received following a pipeline write‑ahead request is not to a pre‑written page, then an interrupt bit is set to 1 and the pipeline read‑ahead or write‑ahead registers are cleared. You must issue a new pipeline write‑ahead request to configure the write logic.

You must use MAP01 commands to write all of the data that is pre‑written before the NAND flash controller returns to the idle state.

Other Supported Commands

MAP01 commands must read or write pages in the same sequence that the pipelined commands were issued to the NAND flash controller. If the host issues multiple pipeline commands, pages must be read or written in the order the pipeline commands were issued. It is not possible to read or write pages for a second pipeline command before completing the first pipeline command. If the pipeline sequence is broken by a MAP01 command, the pipe_cmd_err interrupt is issued, and the flash controller clears the pipeline command queue. The flash controller services the violating incoming MAP01 read or write request with a normal page read or write sequence.

For a multi‑plane device that supports multi‑plane programming, you must set the flag bit of the multiplane_operation register in the config group to 1. In this case, the data is interleaved into page‑size chunks to consecutive blocks.

A pipe_cpyback_cmd_comp interrupt is generated when the NAND flash controller has finished processing a pipeline command and has discarded that command from its queue. At this point of time, the host can send another pipeline command. A pipeline command is popped from the queue, and an interrupt is issued when the flash controller has started processing the last page of pipeline command. Hence, the pipe_cpyback_cmd_comp interrupt is issued prior to the last page load in the case of a pipeline read command and start of data transfer of the last page to be programmed, in the case of a pipeline write command.

An additional program_comp interrupt is generated when the last page program operation completes in the case of a pipeline write command.

If the device command set requires the NAND flash controller to issue a load command for the last page in the pipeline read command, a load_comp interrupt is generated after the last page load operation completes.

The pipeline commands sequence advanced commands in the device, such as cache and multi‑plane. When the NAND flash controller receives a multi‑page read or write pipeline command, it sequences commands sent to the device depending on settings in the following registers in the config group:

  • cache_read_enable
  • cache_write_enable
  • multiplane_operation

For a device that supports cache read sequences, the flag bit of the cache_read_enable register must be set to 1. The NAND flash controller sequences each multi‑page pipeline read command as a cache read sequence. For a device that supports cache program command sequences, cache_write_enable must be set. The flash controller sequences each multi‑page write pipeline command as a cache write sequence.

For a device that has multi‑planes and supports multi‑plane program commands, the NAND flash controller register multiplane_operation, in the config group, must be set. On receiving the multi‑page pipeline write command, the flash controller sequences the device with multi‑plane program commands and expects that the host transfers data to the flash controller in an even‑odd block increment addressing mode.

32 This interrupt status bit is the last to be asserted during a DMA operation to transfer data.
33 Default access mode (0x42) maps to either main (only) or main+spare mode, depending on the value of transfer_spare_reg.
Level Two Title