Visible to Intel only — GUID: sfo1410070078571
Ixiasoft
Visible to Intel only — GUID: sfo1410070078571
Ixiasoft
28.3.3. Reset Interfaces
You can enable the resets on an individual basis through the HPS Clocks and resets tab under the Resets sub tab.
Parameter Name |
Parameter Description |
Interface Name |
---|---|---|
Enable HPS-to-FPGA cold reset output |
Enable interface for HPS-to-FPGA cold reset output |
h2f_cold_reset |
Enable HPS warm reset handshake signals |
Enable an additional pair of reset handshake signals allowing soft logic to notify the HPS when it is safe to initiate a warm reset in the FPGA fabric. |
h2f_warm_reset_handshake |
Enable FPGA-to-HPS debug reset request |
Enable interface for FPGA-to-HPS debug reset request |
f2h_debug_reset_req |
Enable FPGA-to-HPS warm reset request |
Enable interface for FPGA-to-HPS warm reset request |
f2h_warm_reset_req |
Enable FPGA-to-HPS cold reset request |
Enable interface for FPGA-to-HPS cold reset request |
f2h_cold_reset_req |
The SDRAM reset relies on the f2h_cold_reset_reqto be enabled. The reset can be enabled through the Platform Designer (Standard) Resets tab.