Visible to Intel only — GUID: sfo1410070144755
Ixiasoft
Visible to Intel only — GUID: sfo1410070144755
Ixiasoft
A.3. Booting and Configuration Options
SoC initialization includes the booting of the HPS and the configuration of the FPGA fabric and I/O.
- HPS dedicated I/O that are configured by the HPS
- Shared I/O used by the HPS or FPGA and configured by the Intel® Quartus® Prime I/O configuration file.
- FPGA I/O configured by the Intel® Quartus® Prime I/O configuration file.
- Hard memory controller I/O shared by the HPS and FPGA and configured by the Intel® Quartus® Prime I/O configuration file.
Depending on the initialization option you choose, the I/O configuration is handled differently. You can choose one of the three initialization options:
- The HPS boot and FPGA configuration occur separately.
- The HPS boots first and then configures the FPGA.
- The HPS boots from the FPGA after the FPGA is configured.
The following three figures illustrate the possible HPS boot and FPGA configuration schemes. The arrows in the figures denote the data flow direction.
In the figure below, the FPGA configuration and HPS boot can occur separately. The FPGA obtains its configuration image from a non-HPS source. The source is sent to the CSS block which configures the FPGA fabric, FPGA I/O, shared I/O, hard memory controller I/O and other settings. If the hard memory controller or shared I/O are required by the HPS, then the FPGA fabric and I/O (FPGA, shared and hard memory controller) configuration must be complete before the HPS can boot.
The HPS boot ROM obtains its second-stage boot loader from a non-FPGA fabric source. The second-stage boot loader should contain the configuration for the HPS dedicated I/O.
For more information about FPGA configuration, refer to the "FPGA Configuration" section.
In the figure below, the FPGA is configured first through one of its non-HPS configuration sources. The CSS block configures the FPGA fabric as well as the FPGA I/O, shared I/O and hard memory controller I/O. The HPS boot ROM code executes the second-stage boot loader from the FPGA fabric over the HPS-to-FPGA bridge.
You can select a boot from FPGA by setting the BSEL value to 0x1. If the fpga_boot_f fuse is blown then the FPGA is always selected as the boot source. In both cases, when the FPGA is selected as the boot source, the CSEL fuses are ignored and clock configuration is controlled through the second-stage boot loader code in the FPGA.