Visible to Intel only — GUID: sfo1410070173557
Ixiasoft
Visible to Intel only — GUID: sfo1410070173557
Ixiasoft
A.7. FPGA Configuration
You can configure the FPGA portion of the SoC device with non-HPS sources or by utilizing the HPS.
When the HPS handles the initial FPGA configuration, software executing on the HPS writes the configuration image to the FPGA Manager in the HPS. Software can control the configuration process and monitor the FPGA status by accessing the control and status register (CSR) interface in the FPGA Manager.
For the HPS to configure the FPGA, the mode select (MSEL) pins must be set to passive mode (fast or slow). The following table shows the pin encodings for MSEL[2:0] that are available to the HPS. Refer to the Configuration, Design Security, and Remote System Upgrades in Arria 10 Devices document for a comprehensive list of MSEL encodings.
Configuration Scheme allowed through HPS | Power-On Reset (POR) Delay | Valid MSEL[2:0] |
---|---|---|
FPP ( x16, and x32) | Fast | 000 |
Standard | 001 |
There are two types of initial FPGA configuration flows you can choose from when using the HPS to configure the FPGA.
- Full FPGA configuration flow: In this flow, the FPGA fabric, the shared I/O and hard memory controller I/O are configured. After full configuration is complete, the hard memory controller I/O, shared I/O and FPGA I/O are available to the HPS.
- Early I/O release configuration flow: In this flow, all I/O are configured and the HPS shared I/O and hard memory controller I/O are released so that the HPS has immediate access to them. At a later time, the FPGA fabric is configured and the FPGA I/O are released and available to the user design.