EPCQ-L Serial Configuration Devices Datasheet

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ID 683710
Date 5/18/2018
Public
Document Table of Contents
Document Table of Contents x
EPCQ-L Serial Configuration Devices Datasheet
EPCQ-L Serial Configuration Devices Datasheet x
Supported Devices Features Operating Conditions Pin Information Device Package and Ordering Code Memory Array Organization Memory Operations Registers Summary of Operation Codes Power Mode Timing Information Programming and Configuration File Support Document Revision History for EPCQ-L Serial Configuration Devices Datasheet
Operating Conditions x
Absolute Maximum Ratings Recommended Operating Conditions DC Operating Conditions ICC Supply Current Capacitance
Pin Information x
EPCQ-L Device Pin Description
Device Package and Ordering Code x
Package Ordering Code
Memory Array Organization x
Address Range for EPCQ-L256 Address Range for EPCQ-L512 Address Range for EPCQ-L1024
Memory Operations x
Timing Requirements Addressing Mode
Registers x
Status Register Flag Status Register Non-Volatile Configuration Register
Status Register x
Read Status Register Operation (05h) Write Status Register Operation (01h)
Read Status Register Operation (05h) x
Block Protection Bits in EPCQ-L256 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L256 when TB Bit is Set to 1 Block Protection Bits in EPCQ-L512 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L512 when TB Bit is Set to 1 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 1
Flag Status Register x
Read Flag Status Register Operation(70h)
Non-Volatile Configuration Register x
Read Non-Volatile Configuration Register Operation (B5h) Write Non-Volatile Configuration Register Operation (B1h)
Summary of Operation Codes x
4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h) Write Enable Operation (06h) Write Disable Operation (04h) Read Bytes Operation (03h) Fast Read Operation (Bh) Extended Quad Input Fast Read Operation (EBh) Read Device Identification Operation (9Eh or 9Fh) Write Bytes Operation (02h) Extended Quad Input Fast Write Bytes Operation (12h) Erase Bulk Operation (C7h) Erase Die Operation (C4h) Erase Sector Operation (D8h)
Timing Information x
Write Operation Timing Read Operation Timing
EPCQ-L Serial Configuration Devices Datasheet

Write Bytes Operation (02h)

This operation allows bytes to be written to the memory. You must execute the write enable operation before the write bytes operation. After the write bytes operation is completed, the write enable latch bit in the status register is set to 0.

When you execute the write bytes operation, you shift in the write bytes operation code, followed by a 4-byte addressing mode (A[31..0]), and at least one data byte on the DATA0 pin. If the eight LSBs (A[7..0]) are not all 0, all sent data that goes beyond the end of the current page is not written into the next page. Instead, this data is written at the start address of the same page. You must ensure the nCS signal is set low during the entire write bytes operation.

The following figure shows the operation sequence of the write bytes operation.

Figure 15. Write Bytes Operation Timing Diagram

If more than 256 data bytes are shifted into the EPCQ-L device with a write bytes operation, the previously latched data is discarded and the last 256 bytes are written to the page. However, if less than 256 data bytes are shifted into the EPCQ-L device, they are guaranteed to be written at the specified addresses and the other bytes of the same page are not affected.

The device initiates a self-timed write cycle immediately after the nCS signal is driven high. For details about the self-timed write cycle time, refer to tWB in Table 26. You must account for this amount of delay before another page of memory is written. Alternatively, you can check the write in progress bit in the status register by executing the read status operation while the self-timed write cycle is in progress. The write in progress bit is set to 1 during the self-timed write cycle and 0 when it is complete.

Note: You must erase all the memory bytes of EPCQ-L devices before you implement the write bytes operation. You can erase all the memory bytes by executing the erase sector operation in a sector or the erase bulk or erase die operation throughout the entire memory.
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