EPCQ-L Serial Configuration Devices Datasheet

Download PDF
ID 683710
Date 5/18/2018
Public
Document Table of Contents
Document Table of Contents x
EPCQ-L Serial Configuration Devices Datasheet
EPCQ-L Serial Configuration Devices Datasheet x
Supported Devices Features Operating Conditions Pin Information Device Package and Ordering Code Memory Array Organization Memory Operations Registers Summary of Operation Codes Power Mode Timing Information Programming and Configuration File Support Document Revision History for EPCQ-L Serial Configuration Devices Datasheet
Operating Conditions x
Absolute Maximum Ratings Recommended Operating Conditions DC Operating Conditions ICC Supply Current Capacitance
Pin Information x
EPCQ-L Device Pin Description
Device Package and Ordering Code x
Package Ordering Code
Memory Array Organization x
Address Range for EPCQ-L256 Address Range for EPCQ-L512 Address Range for EPCQ-L1024
Memory Operations x
Timing Requirements Addressing Mode
Registers x
Status Register Flag Status Register Non-Volatile Configuration Register
Status Register x
Read Status Register Operation (05h) Write Status Register Operation (01h)
Read Status Register Operation (05h) x
Block Protection Bits in EPCQ-L256 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L256 when TB Bit is Set to 1 Block Protection Bits in EPCQ-L512 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L512 when TB Bit is Set to 1 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 1
Flag Status Register x
Read Flag Status Register Operation(70h)
Non-Volatile Configuration Register x
Read Non-Volatile Configuration Register Operation (B5h) Write Non-Volatile Configuration Register Operation (B1h)
Summary of Operation Codes x
4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h) Write Enable Operation (06h) Write Disable Operation (04h) Read Bytes Operation (03h) Fast Read Operation (Bh) Extended Quad Input Fast Read Operation (EBh) Read Device Identification Operation (9Eh or 9Fh) Write Bytes Operation (02h) Extended Quad Input Fast Write Bytes Operation (12h) Erase Bulk Operation (C7h) Erase Die Operation (C4h) Erase Sector Operation (D8h)
Timing Information x
Write Operation Timing Read Operation Timing
EPCQ-L Serial Configuration Devices Datasheet

Document Revision History for EPCQ-L Serial Configuration Devices Datasheet

Document Version Changes
2018.05.18
  • Updated content of Bit 3 of the Flag Status Register from VPP to Reserved.
  • Updated the overshoot and undershoot note description in Absolute Maximum Ratings table.
2018.03.09 Added data retention feature information.
Date Version Changes
December 2017 2017.12.14
  • Added support for Intel® Cyclone® 10 GX devices.
  • Changed instances of the following:
    • Arria 10 devices to Intel® Arria® 10 devices
    • Stratix 10 devices to Intel® Stratix® 10 devices
    • Quartus Prime software to Intel® Quartus® Prime software
  • Added operation codes for the following operations:
    • Read Status Register Operation Timing Diagram
    • Write Status Register Operation Timing Diagram
    • Read Flag Status Register Operation Timing Diagram
    • Read Non-Volatile Configuration Register Operation Timing Diagram
    • Write Non-Volatile Configuration Register Operation Timing Diagram
    • 4BYTEADDREN Timing Diagram
    • 4BYTEADDREX Timing Diagram
    • Write Enable Operation Timing Diagram
    • Write Disable Operation Timing Diagram
    • Read Bytes Operation Timing Diagram
    • Fast Read Operation Timing Diagram
    • Extended Quad Input Fast Read Operation Timing Diagram
    • Read Device Identification Operation Timing Diagram
    • Write Bytes Operation Timing Diagram
    • Extended Quad Input Fast Write Bytes Operation Sequence
    • Erase Bulk Operation Timing Diagram
    • Erase Sector Operation Timing Diagram
  • Updated the operation code from binary to hex for each operation in the Operation Codes for EPCQ-L Devices table.
  • Updated the Read Flag Status Register Operation Timing Diagram.
  • Updated the note to the fast read and extended quad input fast read operations in the Operation Codes for EPCQ-L Devices table.
May 2017 2017.05.22
  • Added Read flag status register, Dual I/O fast read, and Extended dual input fast write bytes operations.
  • Updated instances of write status operation to write status register operation.
  • Added Flag Status Register Bit Content table.
  • Updated Read Status Register Operations.
  • Updated Read Status Register.
December 2016 2016.12.16
  • Updated address bytes for erase bulk and erase die to 4.
  • Added erase subsector in Operation Codes for EPCQ-L Devices table.
  • Updated tESS Max to 0.8.
October 2016 2016.10.31
  • Added Stratix 10 support.
  • Changed instances of Quartus II to Quartus Prime.
  • Changed instances of USB-Blaster to FPGA USB Download Cable.
  • Changed instances of EthernetBlaster to FPGA Ethernet Download Cable.
May 2016 2016.05.30 Updated Signals for EPCQ-L Devices table by replacing NC with DNU.
March 2016 2016.03.31 Removed 'Preliminary' terms in Address Range for EPCQ-L256, EPCQ-L512 and EPCQ-L1024.
December 2015 2015.12.14 Added link to EPCQ-L packaging information website.
January 2015 2015.01.23
  • Updated the package name to FBGA24.
  • Changed erase bulk operation statement for EPCQ-L256 devices.
  • Added stacked die device in 'Features'.
  • Added Number of die column in 'Supported Devices'.
  • Updated Read Bytes and Fast Read operation description to reflect stacked die properties.
  • Added read non-volatile configuration register.
  • Updated AS x1 dummy clock cycles for non-volatile configuration registers.
  • Updated write non-volatile configuration register 16-bit register value.
June 2014 2014.06.17 Initial release.
Level Two Title