EPCQ-L Serial Configuration Devices Datasheet

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ID 683710
Date 5/18/2018
Public
Document Table of Contents
Document Table of Contents x
EPCQ-L Serial Configuration Devices Datasheet
EPCQ-L Serial Configuration Devices Datasheet x
Supported Devices Features Operating Conditions Pin Information Device Package and Ordering Code Memory Array Organization Memory Operations Registers Summary of Operation Codes Power Mode Timing Information Programming and Configuration File Support Document Revision History for EPCQ-L Serial Configuration Devices Datasheet
Operating Conditions x
Absolute Maximum Ratings Recommended Operating Conditions DC Operating Conditions ICC Supply Current Capacitance
Pin Information x
EPCQ-L Device Pin Description
Device Package and Ordering Code x
Package Ordering Code
Memory Array Organization x
Address Range for EPCQ-L256 Address Range for EPCQ-L512 Address Range for EPCQ-L1024
Memory Operations x
Timing Requirements Addressing Mode
Registers x
Status Register Flag Status Register Non-Volatile Configuration Register
Status Register x
Read Status Register Operation (05h) Write Status Register Operation (01h)
Read Status Register Operation (05h) x
Block Protection Bits in EPCQ-L256 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L256 when TB Bit is Set to 1 Block Protection Bits in EPCQ-L512 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L512 when TB Bit is Set to 1 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 1
Flag Status Register x
Read Flag Status Register Operation(70h)
Non-Volatile Configuration Register x
Read Non-Volatile Configuration Register Operation (B5h) Write Non-Volatile Configuration Register Operation (B1h)
Summary of Operation Codes x
4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h) Write Enable Operation (06h) Write Disable Operation (04h) Read Bytes Operation (03h) Fast Read Operation (Bh) Extended Quad Input Fast Read Operation (EBh) Read Device Identification Operation (9Eh or 9Fh) Write Bytes Operation (02h) Extended Quad Input Fast Write Bytes Operation (12h) Erase Bulk Operation (C7h) Erase Die Operation (C4h) Erase Sector Operation (D8h)
Timing Information x
Write Operation Timing Read Operation Timing
EPCQ-L Serial Configuration Devices Datasheet

Erase Bulk Operation (C7h)

This operation sets all the memory bits to 1or 0xFF. Similar to the write bytes operation, you must execute the write enable operation before the erase bulk operation.

If you are using the EPCQ-L256 device and wish to erase the whole memory of your device, you cannot use the erase die operation and instead must execute the erase bulk operation.

You can implement the erase bulk operation by driving the nCS signal low and then shifting in the erase bulk operation code on the DATA0 pin. The nCS signal must be driven high after the eighth bit of the erase bulk operation code has been latched in.

Figure 17. Erase Bulk Operation Timing Diagram

The device initiates a self-timed erase bulk cycle immediately after the nCS signal is driven high. For details about the self-timed erase bulk cycle time, refer to tWB in Table 26.

You must account for this delay before accessing the memory contents. Alternatively, you can check the write in progress bit in the status register by executing the read status operation while the self-timed erase cycle is in progress. The write in progress bit is set to 1 during the self-timed erase cycle and 0 when it is complete. The write enable latch bit in the status register is reset to 0 before the erase cycle is complete.

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