EPCQ-L Serial Configuration Devices Datasheet

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ID 683710
Date 5/18/2018
Public
Document Table of Contents
Document Table of Contents x
EPCQ-L Serial Configuration Devices Datasheet
EPCQ-L Serial Configuration Devices Datasheet x
Supported Devices Features Operating Conditions Pin Information Device Package and Ordering Code Memory Array Organization Memory Operations Registers Summary of Operation Codes Power Mode Timing Information Programming and Configuration File Support Document Revision History for EPCQ-L Serial Configuration Devices Datasheet
Operating Conditions x
Absolute Maximum Ratings Recommended Operating Conditions DC Operating Conditions ICC Supply Current Capacitance
Pin Information x
EPCQ-L Device Pin Description
Device Package and Ordering Code x
Package Ordering Code
Memory Array Organization x
Address Range for EPCQ-L256 Address Range for EPCQ-L512 Address Range for EPCQ-L1024
Memory Operations x
Timing Requirements Addressing Mode
Registers x
Status Register Flag Status Register Non-Volatile Configuration Register
Status Register x
Read Status Register Operation (05h) Write Status Register Operation (01h)
Read Status Register Operation (05h) x
Block Protection Bits in EPCQ-L256 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L256 when TB Bit is Set to 1 Block Protection Bits in EPCQ-L512 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L512 when TB Bit is Set to 1 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 1
Flag Status Register x
Read Flag Status Register Operation(70h)
Non-Volatile Configuration Register x
Read Non-Volatile Configuration Register Operation (B5h) Write Non-Volatile Configuration Register Operation (B1h)
Summary of Operation Codes x
4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h) Write Enable Operation (06h) Write Disable Operation (04h) Read Bytes Operation (03h) Fast Read Operation (Bh) Extended Quad Input Fast Read Operation (EBh) Read Device Identification Operation (9Eh or 9Fh) Write Bytes Operation (02h) Extended Quad Input Fast Write Bytes Operation (12h) Erase Bulk Operation (C7h) Erase Die Operation (C4h) Erase Sector Operation (D8h)
Timing Information x
Write Operation Timing Read Operation Timing
EPCQ-L Serial Configuration Devices Datasheet

Features

EPCQ-L devices offer the following features:

  • Compatibility with the Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices
  • Native support for active serial (AS) x4
  • Backward compatibility for AS x1 on the Intel® Arria® 10 and Intel® Cyclone® 10 GX devices
  • Low pin count and non-volatile memory
  • 1.8-V operation
  • Stacked die device for the EPCQ-L512 and EPCQ-L1024 devices
  • Manufactured on NOR technology
  • Available in FBGA24 package
  • Reprogrammable memory with more than 100,000 erase or program cycles
  • More than 20 years of data retention
  • Write protection support for memory sectors using status register bits
  • Fast read and extended quad input fast read of the entire memory using a single operation code
  • Write bytes and extended quad input fast write bytes of the entire memory using a single operation code
  • In-system programming (ISP) support with the SRunner software driver
  • ISP support with Intel® FPGA Download Cable II, Intel® FPGA Download Cable, Ethernet Download Cable II, or Ethernet Download Cable download cables
  • By default, the memory array is erased and the bits are set to 1
  • During user mode, you can use the Intel® FPGA ASMI Parallel or Intel® FPGA ASMI Parallel II IP cores to access the EPCQ-L device
  • More than 20 years data retention
Warning: EPCQ-L devices are only compatible with the Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices.
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