Visible to Intel only — GUID: wtw1398490977317
Ixiasoft
Supported Devices
Features
Operating Conditions
Pin Information
Device Package and Ordering Code
Memory Array Organization
Memory Operations
Registers
Summary of Operation Codes
Power Mode
Timing Information
Programming and Configuration File Support
Document Revision History for EPCQ-L Serial Configuration Devices Datasheet
Block Protection Bits in EPCQ-L256 when TB Bit is Set to 0
Block Protection Bits in EPCQ-L256 when TB Bit is Set to 1
Block Protection Bits in EPCQ-L512 when TB Bit is Set to 0
Block Protection Bits in EPCQ-L512 when TB Bit is Set to 1
Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 0
Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 1
4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h)
Write Enable Operation (06h)
Write Disable Operation (04h)
Read Bytes Operation (03h)
Fast Read Operation (Bh)
Extended Quad Input Fast Read Operation (EBh)
Read Device Identification Operation (9Eh or 9Fh)
Write Bytes Operation (02h)
Extended Quad Input Fast Write Bytes Operation (12h)
Erase Bulk Operation (C7h)
Erase Die Operation (C4h)
Erase Sector Operation (D8h)
Visible to Intel only — GUID: wtw1398490977317
Ixiasoft
Extended Quad Input Fast Read Operation (EBh)
This operation is similar to the fast read operation except that the data and addresses are shifted in and out on the DATA0, DATA1, DATA2, and DATA3 pins.
Figure 13. Extended Quad Input Fast Read Operation Timing Diagram
When the device reaches the highest address, the address counter restarts at the beginning of the same die, allowing the read sequence to continue indefinitely. A complete device reading is done by executing the read operation:
- two times for EPCQ-L512 devices
- four times for EPCQ-L1024 devices