EPCQ-L Serial Configuration Devices Datasheet

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ID 683710
Date 5/18/2018
Public
Document Table of Contents
Document Table of Contents x
EPCQ-L Serial Configuration Devices Datasheet
EPCQ-L Serial Configuration Devices Datasheet x
Supported Devices Features Operating Conditions Pin Information Device Package and Ordering Code Memory Array Organization Memory Operations Registers Summary of Operation Codes Power Mode Timing Information Programming and Configuration File Support Document Revision History for EPCQ-L Serial Configuration Devices Datasheet
Operating Conditions x
Absolute Maximum Ratings Recommended Operating Conditions DC Operating Conditions ICC Supply Current Capacitance
Pin Information x
EPCQ-L Device Pin Description
Device Package and Ordering Code x
Package Ordering Code
Memory Array Organization x
Address Range for EPCQ-L256 Address Range for EPCQ-L512 Address Range for EPCQ-L1024
Memory Operations x
Timing Requirements Addressing Mode
Registers x
Status Register Flag Status Register Non-Volatile Configuration Register
Status Register x
Read Status Register Operation (05h) Write Status Register Operation (01h)
Read Status Register Operation (05h) x
Block Protection Bits in EPCQ-L256 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L256 when TB Bit is Set to 1 Block Protection Bits in EPCQ-L512 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L512 when TB Bit is Set to 1 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 1
Flag Status Register x
Read Flag Status Register Operation(70h)
Non-Volatile Configuration Register x
Read Non-Volatile Configuration Register Operation (B5h) Write Non-Volatile Configuration Register Operation (B1h)
Summary of Operation Codes x
4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h) Write Enable Operation (06h) Write Disable Operation (04h) Read Bytes Operation (03h) Fast Read Operation (Bh) Extended Quad Input Fast Read Operation (EBh) Read Device Identification Operation (9Eh or 9Fh) Write Bytes Operation (02h) Extended Quad Input Fast Write Bytes Operation (12h) Erase Bulk Operation (C7h) Erase Die Operation (C4h) Erase Sector Operation (D8h)
Timing Information x
Write Operation Timing Read Operation Timing
EPCQ-L Serial Configuration Devices Datasheet

Read Bytes Operation (03h)

When you execute the read bytes operation, you first shift in the read bytes operation code, followed by a 4-byte addressing mode (A[31..0]). Each address bit is latched in on the rising edge of the DCLK signal. After the address is latched in, the memory contents of the specified address are shifted out serially on the DATA1 pin, beginning with the MSB. When reading back data programmed from a Raw Programming Data File (.rpd), the content is shifted out serially beginning with the LSB. Each data bit is shifted out on the falling edge of the DCLK signal. The maximum DCLK frequency during the read bytes operation is 50 MHz.

Figure 11. Read Bytes Operation Timing Diagram

The first byte address can be at any location. The device automatically increases the address to the next higher address after shifting out each byte of data. When the device reaches the highest address, the address counter restarts at the beginning of the same die, allowing the memory contents to be read out indefinitely until the read bytes operation is terminated by driving the nCS signal high. A complete device reading is done by executing the read operation:

  • two times for EPCQ-L512 devices
  • four times for EPCQ-L1024 devices

If the read bytes operation is shifted in while a write or erase cycle is in progress, the operation is not executed and does not affect the write or erase cycle in progress.

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