Visible to Intel only — GUID: wtw1396921651224
Ixiasoft
Supported Devices
Features
Operating Conditions
Pin Information
Device Package and Ordering Code
Memory Array Organization
Memory Operations
Registers
Summary of Operation Codes
Power Mode
Timing Information
Programming and Configuration File Support
Document Revision History for EPCQ-L Serial Configuration Devices Datasheet
Block Protection Bits in EPCQ-L256 when TB Bit is Set to 0
Block Protection Bits in EPCQ-L256 when TB Bit is Set to 1
Block Protection Bits in EPCQ-L512 when TB Bit is Set to 0
Block Protection Bits in EPCQ-L512 when TB Bit is Set to 1
Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 0
Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 1
4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h)
Write Enable Operation (06h)
Write Disable Operation (04h)
Read Bytes Operation (03h)
Fast Read Operation (Bh)
Extended Quad Input Fast Read Operation (EBh)
Read Device Identification Operation (9Eh or 9Fh)
Write Bytes Operation (02h)
Extended Quad Input Fast Write Bytes Operation (12h)
Erase Bulk Operation (C7h)
Erase Die Operation (C4h)
Erase Sector Operation (D8h)
Visible to Intel only — GUID: wtw1396921651224
Ixiasoft
EPCQ-L Serial Configuration Devices Datasheet
Section Content
Supported Devices
Features
Operating Conditions
Pin Information
Device Package and Ordering Code
Memory Array Organization
Memory Operations
Registers
Summary of Operation Codes
Power Mode
Timing Information
Programming and Configuration File Support
Document Revision History for EPCQ-L Serial Configuration Devices Datasheet