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1. Intel® Agilex™ Configuration User Guide
2. Intel® Agilex™ Configuration Details
3. Intel® Agilex™ Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Intel® Agilex™ Configuration Features
7. Intel® Agilex™ Debugging Guide
8. Intel® Agilex™ Configuration User Guide Archives
9. Document Revision History for the Intel® Agilex™ Configuration User Guide
2.1. Intel® Agilex™ Configuration Timing Diagram
2.2. Configuration Flow Diagram
2.3. Device Response to Configuration and Reset Events
2.4. Additional Clock Requirements for HPS and Transceivers
2.5. Intel® Agilex™ Configuration Pins
2.6. Configuration Clocks
2.7. Intel® Agilex™ Configuration Time Estimation
2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
3.1.7.4.1. PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins
Create a pfl_clk clock and a generated AVST_CLK clock
Set output delay for PFL II IP output pins
Setting a false path
3.1.7.4.2. PFL II IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. PFL II IP Recommended Design Constraints for using CFI Flash
3.1.7.4.4. PFL II IP Recommended Constraints for Other Input Pins
3.1.7.4.5. PFL II IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Intel® Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Intel® Agilex™ Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. Configuration File Format Differences
7.5. Understanding SEUs
7.6. Reading the Unique 64-Bit CHIP ID
7.7. E-Tile Transceivers May Fail To Configure
7.8. Understanding and Troubleshooting Configuration Pin Behavior
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3.1.7.4.1. PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins
Create a pfl_clk clock and a generated AVST_CLK clock
Example below creates a pfl_clk clock running at 50 MHz, supplied by the clk_50m_sysmax input clock.
set pfl_clk_period 20.000
create_clock -name {clk_50m_sysmax} -period $pfl_clk_period [get_ports {clk_50m_sysmax}]
create_generated_clock -name AVST_CLK -source [get_ports {clk_50m_sysmax}] [get_ports {avst_clk}]
Set output delay for PFL II IP output pins
Example below sets the output delay for the AvST_DATA and AvST_VALID pins.
set avst_data_tracemax 0.250
set avst_data_tracemin 0.000
set avst_clk_tracemax 0.250
set avst_clk_tracemin 0.000
set fpga_Tsu 2.100
set fpga_Th 0.100
set fpga_out_max_dly [expr $avst_data_tracemax + $fpga_Tsu - $avst_clk_tracemin]
set fpga_out_min_dly [expr $avst_data_tracemin - $fpga_Th - $avst_clk_tracemax]
set_output_delay -add_delay -max -clock [get_clocks {AVST_CLK}] $fpga_out_max_dly [get_ports {avst_d[*] avst_valid}]
set_output_delay -add_delay -min -clock [get_clocks {AVST_CLK}] $fpga_out_min_dly [get_ports {avst_d[*] avst_valid}]
Setting a false path
You can set the AVST_READY input pin to a false path since this pin is not synchronous to the AVST_CLK clock. The host must synchronize the AVST_READY signal to the AVST_CLK signal using a 2-stage register synchronizer.
set_false_path -from [get_ports {avst_ready}] -to *