Visible to Intel only — GUID: zhz1494232281358
Ixiasoft
1. Intel® Agilex™ Configuration User Guide
2. Intel® Agilex™ Configuration Details
3. Intel® Agilex™ Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Intel® Agilex™ Configuration Features
7. Intel® Agilex™ Debugging Guide
8. Intel® Agilex™ Configuration User Guide Archives
9. Document Revision History for the Intel® Agilex™ Configuration User Guide
2.1. Intel® Agilex™ Configuration Timing Diagram
2.2. Configuration Flow Diagram
2.3. Device Response to Configuration and Reset Events
2.4. Additional Clock Requirements for HPS and Transceivers
2.5. Intel® Agilex™ Configuration Pins
2.6. Configuration Clocks
2.7. Intel® Agilex™ Configuration Time Estimation
2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
3.1.7.4.1. PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. PFL II IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. PFL II IP Recommended Design Constraints for using CFI Flash
3.1.7.4.4. PFL II IP Recommended Constraints for Other Input Pins
3.1.7.4.5. PFL II IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Intel® Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Intel® Agilex™ Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. Configuration File Format Differences
7.5. Understanding SEUs
7.6. Reading the Unique 64-Bit CHIP ID
7.7. E-Tile Transceivers May Fail To Configure
7.8. Understanding and Troubleshooting Configuration Pin Behavior
Visible to Intel only — GUID: zhz1494232281358
Ixiasoft
5.3.2. Error Code Responses
Value (Hex) | Error Code Response | Description | |||
---|---|---|---|---|---|
0 | OK | Indicates that the command completed successfully. A command may erroneously return the OK status if a command, such as QSPI_READ is partially successful. |
|||
1 | INVALID_COMMAND | Indicates that the currently loaded boot ROM cannot decode or recognize the command code. | |||
3 | UNKNOWN_COMMAND | Indicates that the currently loaded firmware cannot decode the command code. | |||
4 | INVALID_COMMAND_PARAMETERS | Indicates that the command is incorrectly formatted. For example, the length field setting in header is not valid. | |||
6 | COMMAND_INVALID_ON_SOURCE | Indicates that the command is from a source for which it is not enabled. | |||
8 | CLIENT_ID_NO_MATCH | Indicates that the Client ID cannot complete the request to close the exclusive access to quad SPI. The Client ID does not match the existing client with the current exclusive access to quad SPI. | |||
9 | INVALID_ADDRESS | The address is invalid. This error indicates one of the following conditions:
|
|||
A | AUTHENTICATION_FAIL | Indicates the configuration bitstream signature authentication failure. | |||
B | TIMEOUT | This error indicates time out due to the following conditions:
|
|||
C | HW_NOT_READY | Indicates one of the following conditions:
|
|||
D | HW_ERROR | Indicates that the command completed unsuccessfully due to unrecoverable hardware error. | |||
80 - 8F | COMMAND_SPECIFIC_ERROR | Indicates a command specific error due to an SDM command you used. | |||
SDM Command | Error Name | Error code | Description | ||
GET_CHIPID | EFUSE_SYSTEM_FAILURE | 0x82 | Indicates that the eFuse cache pointer is invalid. | ||
QSPI_OPEN/ QSPI_CLOSE/ QSPI_SET_CS/ QSPI_READ_DEVICE_REG/ QSPI_WRITE_DEVICE_REG/ QSPI_SEND_DEVICE_OP/ QSPI_READ |
QSPI_HW_ERROR | 0x80 | Indicates QSPI flash memory error. This error indicates one of the following conditions:
|
||
QSPI_ALREADY_OPEN | 0x81 | Indicates that the client's exclusive access to QSPI flash via QSPI_OPEN command is already open. | |||
100 | NOT_CONFIGURED | Indicates that the device is not configured. | |||
1FF | ALT_SDM_MBOX_RESP_DEVICE_ BUSY | Indicates that the device is busy due to following use cases:
|
|||
2FF | ALT_SDM_MBOX_RESP_NO_VALID_RESP_AVAILABLE | Indicates that there is no valid response available. | |||
3FF | ALT_SDM_MBOX_RESP_ERROR | General Error. |