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1. Intel® Agilex™ Configuration User Guide
2. Intel® Agilex™ Configuration Details
3. Intel® Agilex™ Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Intel® Agilex™ Configuration Features
7. Intel® Agilex™ Debugging Guide
8. Intel® Agilex™ Configuration User Guide Archives
9. Document Revision History for the Intel® Agilex™ Configuration User Guide
2.1. Intel® Agilex™ Configuration Timing Diagram
2.2. Configuration Flow Diagram
2.3. Device Response to Configuration and Reset Events
2.4. Additional Clock Requirements for HPS and Transceivers
2.5. Intel® Agilex™ Configuration Pins
2.6. Configuration Clocks
2.7. Intel® Agilex™ Configuration Time Estimation
2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
3.1.7.4.1. PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. PFL II IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. PFL II IP Recommended Design Constraints for using CFI Flash
3.1.7.4.4. PFL II IP Recommended Constraints for Other Input Pins
3.1.7.4.5. PFL II IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Intel® Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Intel® Agilex™ Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. Configuration File Format Differences
7.5. Understanding SEUs
7.6. Reading the Unique 64-Bit CHIP ID
7.7. E-Tile Transceivers May Fail To Configure
7.8. Understanding and Troubleshooting Configuration Pin Behavior
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7.1. Configuration Debugging Checklist
Work through this checklist to identify issues that may result in operational failures.
Checklist Item | Complete? | ||
---|---|---|---|
1 | Verify that all configuration resistors are correctly connected (MSEL, nCONFIG, nSTATUS, CONF_DONE, INIT_DONE, PWRMGT_SDA, PWRMGT_SCL). | ☐ | |
2 | Verify that you are following the correct power-up and power-down sequences. | ☐ | |
3 | Verify that the SDM I/Os assignments are correct by checking the Intel® Quartus® Prime Compilation QSF and Fitter reports. | ☐ | |
4 | For SmartVID devices (-V or -E), ensure that all PMBus pins are connected to Intel® Agilex™ device. | ☐ | |
5 | Verify that SmartVID settings follow the recommendations in the Intel® Agilex™ Power Management User Guide | ☐ | |
6 | Verify that the Intel® Agilex™ -V or -E device has its own voltage regulator module for VCC, VCCP, VCCL_HPS, and VCCPLLDIG_HPS | ☐ | |
7 | After configuration are the nCONFIG, nSTATUS, CONF_DONE, and INIT_DONE pins high? For more information about configuration status, refer to the Understanding Configuration Status Using quartus_pgm Command section. |
☐ | |
8 | Is the SDM operating Boot ROM code or configuration firmware? |
☐ | |
9 | Are the MSEL pins correctly connected on board? | ☐ | |
10 | For designs that use transceivers, HBM2, PCIe* , or EMIF, are the reference clocks stable and free running before configuration begins? | ☐ | |
11 | Verify that selected clocks match the frequency setting specified in the Intel® Quartus® Prime software during configuration. | ☐ | |
12 | Does your design include the Reset Release IP? | ☐ | |
13 | To avoid configuration failures, disconnect the PMBus regulator’s JTAG download cable before configuring Intel® Agilex™ -V devices. | ☐ | |
14 | Verify that the Intel® Agilex™ device has exited POR by checking nCONFIG, nSTATUS, CONF_DONE and INIT_DONE pins using an oscilloscope. | ☐ | |
15 | Is the configuration clock source chosen appropriately? You can use an internal oscillator or the OSC_CLK_1 pin. | ☐ | |
16 | For designs driving the OSC_CLK_1 pin is the frequency 25, 100, or 125 MHz? | ☐ | |
17 | For Intel® Agilex™ SX parts ensure that the HPS and EMIF IOPLL reference clocks are stable and free running before configuration begins. The actual frequency should match the setting specified in Platform Designer. | ☐ | |
18 | Are proper slave addresses set for the PMBus voltage regulator modules using the Intel® Quartus® Prime Software? | ☐ | |
19 | For designs that use 3 V I/0, verify that the transceiver tiles are powered up before configuration begins. | ☐ |
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