4.2.1. 5G LDPC-V Receiver Signals
All signals are synchronous to clk.
Figure 12. Receiver Top-level Block DiagramThis figure does not show the Avalon streaming interface signals
.
| Name | Direction | Description |
|---|---|---|
| clk | Input | Clock. All signals are synchronous to clk. |
| rstn | Input | Reset, active-low. Assert for at least for 10 clock cycles. Do not send data or parameters when reset is asserted |
| i_ldpc_paras | Input | Align with i_sink_cb_sop. [0] is base graph (BG) (1 bit):
[6:1] is Zc_idx (6 bits), the index of lifting factor Zc. Choose Zc from Table 5.3.2-1 of TS38.212. Look up the index of Zc in the Lifting Factor table.. [7] is use_crc (1 bit)
[17:8] is the number of null bits (10 bits). Plug in the value of K-K’, where K=22Zc(BG1) or 10Zc(BG2). Check the definition of K and K’ in section 5.2.2 in TS 38.212 [20:18] is the code rate index (3 bits). The Code Rate Index table shows the code rate choices supported by the LDPC encoder and decoder IP. The code rate is not the target code rate. [23:21] is Qm_idx (3 bits):
[44:24] is E (21 bits), the output length of the rate matcher, or equivalently, input length of the de-rate matcher [59:45] is k0 position (15 bits).Calculate k0 based on Table 5.4.2.1-2 of TS 38.212 [65:60] is max_iter (6 bits), the maximum number of iterations of LDPC decoding. [66] is use_harq (1 bit)
[81:67] is cb_old_len (15 bit), the length of the previously combined code block already stored in DRR. cb_old_len should be less than or equal to codeword_length of the current frame and the max codeword_length of all the previous frames (first frame is when use_harq = 0). [109:82] is cb_ddr_addr (28 bit), the base address to DDR for the combined code block [110] is et_dis (1 bit), the decoder early termination disable.
[111] is red_synd (1 bit), the decoder reduce syndrome checks
[124:112] is the limited circular buffer size. |
| i_sink_data | Input | 16 LLRs x LLR_W bits per LLR [LLR_W-1:0]: LLR seq# 0, [LLR_W*2-1:LLR_W]: LLR seq #1,... |
| i_sink_valid | Input | Qualifies the i_sink_data signal When i_sink_valid is not asserted, the IP stops processing input until i_sink_valid signal is reasserted. Asserted when o_sink_ready is asserted. |
| i_sink_cb_sop | Input | Indicates the start of an incoming packet You cannot have two valid SOPs in any four consecutive clock cycles |
| i_sink_cb_eop | Input | Indicates the end of an incoming packet |
| o_sink_ready | Output | Indicates that the receiver is ready to receive data in the next clock cycle. Ignore when rstn is asserted. The IP can backpressure incoming data by deasserting this signal: when you see o_sink_ready==0, deassert i_sink_valid in the next clock cycle |
| o_source_data | Output | LDPC decoded hard bits, including code block CRC bit, not including NULL padding (K-K'). data[0] -> bit0, data[1] -> bit1,…,data[31] -> bit31 |
| o_source_valid | Output | The receiver asserts this signal when o_source_data holds valid data |
| o_source_cb_sop | Output | The receiver asserts this signal to indicate the start of a packet |
| o_source_cb_eop | Output | The receiver asserts this signal to indicate the end of a packet |
| o_ldpc_metrics | Output |
[0] is source_crc_pass (1 bit)
[1] is source_et_pass (1 bit): refer to 5G LDPC Intel FPGA IP User Guide, align with SOP [7:2] is source_iter (6 bits): refer to 5G LDPC Intel FPGA IP User Guide, align with SOP. |
| avmm_address | Output | DDR SDRAM 28 bits address (Avalon memory-mapped master) |
| avmm_read | Output | DDR read request (Avalon memory-mapped master) |
| avmm_readdata | Input | DDR read data with 128*LLR_W bit width (Avalon memory-mapped master) |
| avmm_readdatavalid | Input | DDR read data valid (Avalon memory-mapped master) |
| avmm_write | Output | DDR write request (Avalon memory-mapped master) |
| avmm_writedata | Output | DDR write data with 128*LLR_W bit width (Avalon memory-mapped master) |
| avmm_waitrequest | Input | DDR wait request (Avalon memory-mapped master) |