5G LDPC-V Intel® FPGA IP User Guide

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ID 683670
Date 7/19/2021
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Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC-V Intel® FPGA IP 2. Getting Started with the 5G LDPC-V Intel® FPGA IP 3. Designing with the 5G LDPC-V Intel® FPGA IP 4. 5G LDPC-V Intel® FPGA IP Functional Description 5. 5G LPDC-V IP User Guide Archive 6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide
1. About the 5G LDPC-V Intel® FPGA IP x
1.1. 5G LDPC-V Intel® FPGA IP Features 1.2. 5G LDPC-V Intel® FPGA IP Device Family Support 1.3. Release Information for the 5G LDPC-V Intel® FPGA IP 1.4. 5G LDPC-V Performance and Resource Utilization
2. Getting Started with the 5G LDPC-V Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC-V IP Timeout Behavior
3. Designing with the 5G LDPC-V Intel® FPGA IP x
3.1. 5G LDPC-V IP Directory Structure 3.2. Generating a 5G LPDC-V IP 3.3. Simulating the 5G LDPC-V IP 3.4. 5G LDPC-V Simulation Results
4. 5G LDPC-V Intel® FPGA IP Functional Description x
4.1. 5G LDPC-V Transmitter Functional Description 4.2. 5G LDPC-V Receiver Functional Description 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.4. 5G LDPC-V Throughput and Latency
4.1. 5G LDPC-V Transmitter Functional Description x
4.1.1. 5G LDPC-V Transmitter Signals 4.1.2. 5G LDPC-V Lifting Factor and Code Rate Indexes
4.2. 5G LDPC-V Receiver Functional Description x
4.2.1. 5G LDPC-V Receiver Signals
1. About the 5G LDPC-V Intel® FPGA IP
2. Getting Started with the 5G LDPC-V Intel® FPGA IP
3. Designing with the 5G LDPC-V Intel® FPGA IP
4. 5G LDPC-V Intel® FPGA IP Functional Description
5. 5G LPDC-V IP User Guide Archive
6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide

1.4. 5G LDPC-V Performance and Resource Utilization

Table 2.  Performance and Resource UtilizationShows the performance with Intel® Quartus® Prime Pro Edition v21.2.
Family Speed Grade Device Component Ave fMAX (reduced 15% for margin) (MHz) ALM M20K DSP Blocks
Intel Agilex 2 AGFB014R24B2I2V Transmitter 606 14.7k 27 2
Receiver (6-bit LLR) 497 79.5k 907 1
Receiver (5-bit LLR) 504 71.9k 797 1
Intel Stratix 10 2 1SG280HU2F50E2VG Transmitter 401 12.5k 27 2
Receiver (6-bit LLR) 375 80.1k 907 1
Receiver (5-bit LLR) 385 72.1k 797 1
Intel Stratix 10 2L 1SG280HU2F50E2LG Transmitter 380 12.5k 27 2
Receiver (6-bit LLR) 360 80.1k 907 1
Receiver (5-bit LLR) 358 72.1k 797 1
Intel Arria 10 1 10AT115S1F45E1SG Transmitter 363 12.2k 27 2
Receiver (6-bit LLR) 286 67.4k 880 1
Receiver (5-bit LLR) 299 70.0k 774 1
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