5G LDPC-V Intel® FPGA IP User Guide

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ID 683670
Date 7/19/2021
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Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC-V Intel® FPGA IP 2. Getting Started with the 5G LDPC-V Intel® FPGA IP 3. Designing with the 5G LDPC-V Intel® FPGA IP 4. 5G LDPC-V Intel® FPGA IP Functional Description 5. 5G LPDC-V IP User Guide Archive 6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide
1. About the 5G LDPC-V Intel® FPGA IP x
1.1. 5G LDPC-V Intel® FPGA IP Features 1.2. 5G LDPC-V Intel® FPGA IP Device Family Support 1.3. Release Information for the 5G LDPC-V Intel® FPGA IP 1.4. 5G LDPC-V Performance and Resource Utilization
2. Getting Started with the 5G LDPC-V Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC-V IP Timeout Behavior
3. Designing with the 5G LDPC-V Intel® FPGA IP x
3.1. 5G LDPC-V IP Directory Structure 3.2. Generating a 5G LPDC-V IP 3.3. Simulating the 5G LDPC-V IP 3.4. 5G LDPC-V Simulation Results
4. 5G LDPC-V Intel® FPGA IP Functional Description x
4.1. 5G LDPC-V Transmitter Functional Description 4.2. 5G LDPC-V Receiver Functional Description 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.4. 5G LDPC-V Throughput and Latency
4.1. 5G LDPC-V Transmitter Functional Description x
4.1.1. 5G LDPC-V Transmitter Signals 4.1.2. 5G LDPC-V Lifting Factor and Code Rate Indexes
4.2. 5G LDPC-V Receiver Functional Description x
4.2.1. 5G LDPC-V Receiver Signals
1. About the 5G LDPC-V Intel® FPGA IP
2. Getting Started with the 5G LDPC-V Intel® FPGA IP
3. Designing with the 5G LDPC-V Intel® FPGA IP
4. 5G LDPC-V Intel® FPGA IP Functional Description
5. 5G LPDC-V IP User Guide Archive
6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide

4.4. 5G LDPC-V Throughput and Latency

Throughput and latency scales linearly with the clock frequency.
Table 11.  5G LDPC-V Transmitter Throughput and Latency Encoding chain clock frequency =268 MHz (arbitrary); Qm = 2; k0 = 0. Throughput is the number of user bits divided by the time difference between two consecutive sink SOPs when the design is running at full capacity. Latency is the time difference between the sink SOP and source SOP when the design is ready to process the input immediately.

BG

Z

E

 Throughput (Gbps)

Latency (µs)
0 12 316 0.220 2.526
0 12 474 0.220 2.593
0 12 632 0.220 2.664
0 12 790 0.220 2.731
0 12 948 0.220 2.731
0 12 1106 0.220 2.731
0 12 1264 0.220 2.731
0 12 1422 0.220 2.731
0 12 1580 0.220 2.731
0 192 5068 3.359 3.787
0 192 7602 3.359 4.377
0 192 10136 3.127 4.966
0 192 12670 2.573 5.556
0 192 15204 2.310 5.556
0 192 17738 1.990 5.556
0 192 20272 1.747 5.556
0 192 22806 1.557 5.556
0 192 25340 1.405 5.556
0 384 10136 6.254 4.743
0 384 15204 4.371 5.929
0 384 20272 3.359 7.108
0 384 25340 2.728 8.287
0 384 30408 2.346 8.287
0 384 35476 2.016 8.287
0 384 40544 1.767 8.287
0 384 45612 1.572 8.287
0 384 50680 1.417 8.287
1 12 240 0.155 1.519
1 12 360 0.155 1.571
1 12 480 0.155 1.616
1 12 600 0.155 1.672
1 12 720 0.155 1.672
1 12 840 0.155 1.672
1 12 960 0.155 1.672
1 12 1080 0.155 1.672
1 12 1200 0.155 1.672
1 192 3840 2.486 2.396
1 192 5760 2.297 2.843
1 192 7680 1.812 3.291
1 192 9600 1.496 3.739
1 192 11520 1.376 3.739
1 192 13440 1.186 3.739
1 192 15360 1.042 3.739
1 192 17280 0.929 3.739
1 192 19200 0.838 3.739
1 384 7680 3.702 3.201
1 384 11520 2.586 4.097
1 384 15360 1.987 4.993
1 384 19200 1.613 5.888
1 384 23040 1.402 5.888
1 384 26880 1.205 5.888
1 384 30720 1.057 5.888
1 384 34560 0.941 5.888
1 384 38400 0.848 5.888
Table 12.  5G LDPC-V Receiver Throughput and LatencyDecoding chain clock frequency = 268 MHz (arbitrary), Qm = 2, k0 = 0, Decoder Iter.= 8. Throughput is the number of decoded bits divided by the time difference between two consecutive sink SOPs when the design is running at full capacity. Latency is the time difference between the sink SOP and source SOP when the design is ready to process the input immediately.

BG

Z

E

Throughput (Gbps)

Latency (µs)
0 12 316 0.086 17.668
0 12 474 0.040 39.985
0 12 632 0.032 49.951
0 12 790 0.027 58.530
0 12 948 0.027 58.567
0 12 1106 0.027 58.604
0 12 1264 0.027 58.937
0 12 1422 0.027 57.955
0 12 1580 0.027 58.063
0 192 5068 1.374 16.280
0 192 7602 0.644 38.806
0 192 10136 0.512 47.541
0 192 12670 0.430 55.481
0 192 15204 0.431 51.545
0 192 17738 0.430 50.907
0 192 20272 0.430 51.235
0 192 22806 0.429 50.276
0 192 25340 0.430 48.806
0 384 10136 2.748 15.507
0 384 15204 1.288 36.190
0 384 20272 1.022 43.489
0 384 25340 0.859 50.769
0 384 30408 0.861 47.310
0 384 35476 0.859 49.108
0 384 40544 0.859 48.836
0 384 45612 0.771 48.104
0 384 50680 0.696 49.993
1 12 240 0.050 17.317
1 12 360 0.032 25.922
1 12 480 0.020 39.414
1 12 600 0.020 39.500
1 12 720 0.020 39.459
1 12 840 0.020 39.448
1 12 960 0.020 39.388
1 12 1080 0.020 39.470
1 12 1200 0.020 39.433
1 192 3840 0.792 17.448
1 192 5760 0.506 26.604
1 192 7680 0.315 40.071
1 192 9600 0.314 39.698
1 192 11520 0.314 39.448
1 192 13440 0.313 38.840
1 192 15360 0.312 39.004
1 192 17280 0.312 38.619
1 192 19200 0.311 38.287
1 384 7680 1.571 17.522
1 384 11520 1.004 26.922
1 384 15360 0.625 40.108
1 384 19200 0.627 39.903
1 384 23040 0.622 39.231
1 384 26880 0.583 38.899
1 384 30720 0.513 39.940
1 384 34560 0.458 40.437
1 384 38400 0.414 40.799
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