5G LDPC-V Intel® FPGA IP User Guide

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ID 683670
Date 7/19/2021
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Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC-V Intel® FPGA IP 2. Getting Started with the 5G LDPC-V Intel® FPGA IP 3. Designing with the 5G LDPC-V Intel® FPGA IP 4. 5G LDPC-V Intel® FPGA IP Functional Description 5. 5G LPDC-V IP User Guide Archive 6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide
1. About the 5G LDPC-V Intel® FPGA IP x
1.1. 5G LDPC-V Intel® FPGA IP Features 1.2. 5G LDPC-V Intel® FPGA IP Device Family Support 1.3. Release Information for the 5G LDPC-V Intel® FPGA IP 1.4. 5G LDPC-V Performance and Resource Utilization
2. Getting Started with the 5G LDPC-V Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC-V IP Timeout Behavior
3. Designing with the 5G LDPC-V Intel® FPGA IP x
3.1. 5G LDPC-V IP Directory Structure 3.2. Generating a 5G LPDC-V IP 3.3. Simulating the 5G LDPC-V IP 3.4. 5G LDPC-V Simulation Results
4. 5G LDPC-V Intel® FPGA IP Functional Description x
4.1. 5G LDPC-V Transmitter Functional Description 4.2. 5G LDPC-V Receiver Functional Description 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.4. 5G LDPC-V Throughput and Latency
4.1. 5G LDPC-V Transmitter Functional Description x
4.1.1. 5G LDPC-V Transmitter Signals 4.1.2. 5G LDPC-V Lifting Factor and Code Rate Indexes
4.2. 5G LDPC-V Receiver Functional Description x
4.2.1. 5G LDPC-V Receiver Signals
1. About the 5G LDPC-V Intel® FPGA IP
2. Getting Started with the 5G LDPC-V Intel® FPGA IP
3. Designing with the 5G LDPC-V Intel® FPGA IP
4. 5G LDPC-V Intel® FPGA IP Functional Description
5. 5G LPDC-V IP User Guide Archive
6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide

3.1. 5G LDPC-V IP Directory Structure

The IP includes a c_model, matlab, src, simulation_scripts, and test_data directory.
Table 4.  Files in the c_model Directory

Other .c and .cpp files in c_model are obfuscated models of different blocks.

File Description
ldpc5g_tx_chain.c Clear-text transmitter chain wrapper
ldpc5g_tx_chain_test.c Clear-text transmitter chain testbench
ldpc5g_rx_chain.cpp Clear-text receiver chain wrapper
ldpc5g_rx_chain_test.cpp Clear-text receiver chain testbench
ldpc5g_gen_tc.c Clear-text test cases for transmitter and receiver chain
Table 5.  Directories in the src Directory
File Description
aldec Encrypted RTL files for Aldec
cadence Encrypted RTL files for NCSim
mentor Encrypted RTL files for ModelSim
synopsys Encrypted RTL files for VCS
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