5G LDPC-V Intel® FPGA IP User Guide

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ID 683670
Date 7/19/2021
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Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC-V Intel® FPGA IP 2. Getting Started with the 5G LDPC-V Intel® FPGA IP 3. Designing with the 5G LDPC-V Intel® FPGA IP 4. 5G LDPC-V Intel® FPGA IP Functional Description 5. 5G LPDC-V IP User Guide Archive 6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide
1. About the 5G LDPC-V Intel® FPGA IP x
1.1. 5G LDPC-V Intel® FPGA IP Features 1.2. 5G LDPC-V Intel® FPGA IP Device Family Support 1.3. Release Information for the 5G LDPC-V Intel® FPGA IP 1.4. 5G LDPC-V Performance and Resource Utilization
2. Getting Started with the 5G LDPC-V Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC-V IP Timeout Behavior
3. Designing with the 5G LDPC-V Intel® FPGA IP x
3.1. 5G LDPC-V IP Directory Structure 3.2. Generating a 5G LPDC-V IP 3.3. Simulating the 5G LDPC-V IP 3.4. 5G LDPC-V Simulation Results
4. 5G LDPC-V Intel® FPGA IP Functional Description x
4.1. 5G LDPC-V Transmitter Functional Description 4.2. 5G LDPC-V Receiver Functional Description 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.4. 5G LDPC-V Throughput and Latency
4.1. 5G LDPC-V Transmitter Functional Description x
4.1.1. 5G LDPC-V Transmitter Signals 4.1.2. 5G LDPC-V Lifting Factor and Code Rate Indexes
4.2. 5G LDPC-V Receiver Functional Description x
4.2.1. 5G LDPC-V Receiver Signals
1. About the 5G LDPC-V Intel® FPGA IP
2. Getting Started with the 5G LDPC-V Intel® FPGA IP
3. Designing with the 5G LDPC-V Intel® FPGA IP
4. 5G LDPC-V Intel® FPGA IP Functional Description
5. 5G LPDC-V IP User Guide Archive
6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide

3.2. Generating a 5G LPDC-V IP

To include the IP in a design, generate the IP in the Intel® Quartus® Prime software. Or optionally, you can generate a design example that includes the generated 5G LDPC-V IP, a C model, a MATLAB model, simulation scripts, and test data. The software generates no hardware example in Generate Example Design.
  1. Create a New Intel® Quartus® Prime project
  2. Open IP Catalog.
  3. Select DSP > Error Detection and Correction > 5G LDPC-V and click Add
  4. Enter a name for your IP variant and click Create.
    Figure 4. IP Variant File Name
    The name is for both the top-level RTL module and the corresponding .ip file.
    The parameter editor for this IP appears.
  5. Choose your parameters.
    Table 6.  5G LDPC-V Parameters
    Parameter Name Values Description
    Mode

    Rx chain

    Tx chain

    		 Select between receiver or transmitter.
    LLR_W (receiver only)

    5

    6

    		 Input LLR bitwidth.

    LLR_W=5, gives 3 integral bits and 2 fractional bits, i.e. a range of [-4.0, 3.75]

    LLR_W=6, gives 4 integral bits and 2 fractional bits, i.e. a range of [-8.0, 7.75]

    NUM_DECODERS

    (receiver only)

    1

    2

    		 The number of decoders that the IP builds.
    MAX_LF_DECODER1

    (receiver only)

    96

    128

    192

    		 The maximum lifting factor for the packet that the second decoder can process. Only valid when NUM_DECODERS is to 2
    Figure 5. 5G LDPC Parameter Editor
  6. For an optional design example, click Generate Example Design
    The software creates a design example of the transmitter or receiver.
    Figure 6. Design Example Directory Structure
  7. Click Generate HDL.
Intel® Quartus® Prime generates the RTL and the files necessary to instantiate the IP in your design and synthesize it.
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