Visible to Intel only — GUID: vdz1655085715720
Ixiasoft
2.3.3. Reset and Debug Signals
Interface | Type | Description |
---|---|---|
reset | Reset | A global hardware reset input signal that forces the Nios® V processor to reset immediately. |
dbg_reset_out | Reset | An optional reset output signal which appear after you enable both Enable Debug and Enable Reset from Debug Module parameters.
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ndm_reset_in | Reset | An optional reset input signal which appear after you enable both Enable Debug and Enable Reset from Debug Module parameters.
|
cpu_resetreq | Conduit | An optional local reset ports which appear after you enable Add Reset Request Interface parameter. The signal consists of an input resetreq signal and an output ack signal that trigger the Nios® V processor to reset without affecting other components in a Nios® V processor system.
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Figure 3. Nios® V Processor Reset Network