Nios® V Processor Reference Manual

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ID 683632
Date 10/31/2022
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Nios® V/m Processor 3. Nios V Processor Reference Manual Archives 4. Document Revision History for the Nios® V Processor Reference Manual
1. Overview x
1.1. Intel® Quartus® Prime Software Support
2. Nios® V/m Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation
2.3. Processor Architecture x
2.3.1. General-Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Reset and Debug Signals 2.3.4. Control and Status Registers 2.3.5. Exception Controller 2.3.6. Interrupt Controller 2.3.7. Memory and I/O Organization 2.3.8. RISC-V based Debug Module
2.3.6. Interrupt Controller x
2.3.6.1. Timer and Software Interrupt Module
2.3.7. Memory and I/O Organization x
2.3.7.1. Instruction and Data Buses
2.3.7.1. Instruction and Data Buses x
2.3.7.1.1. Instruction Manager Port 2.3.7.1.2. Data Manager Port 2.3.7.1.3. Address Map
2.3.8. RISC-V based Debug Module x
2.3.8.1. Debug Mode 2.3.8.2. Halt from Debug Module 2.3.8.3. Trigger 2.3.8.4. Abstract Commands in Debug Mode 2.3.8.5. Hardware/Software Interface
2.4. Programming Model x
2.4.1. Privilege Levels 2.4.2. Control and Status Registers (CSR) Mapping
2.4.1. Privilege Levels x
2.4.1.1. Machine Mode (M-mode) 2.4.1.2. Debug Mode (D-mode)
2.4.2. Control and Status Registers (CSR) Mapping x
2.4.2.1. Control and Status Register Field
2.5. Core Implementation x
2.5.1. Instruction Set Reference
1. Overview
2. Nios® V/m Processor
3. Nios V Processor Reference Manual Archives
4. Document Revision History for the Nios® V Processor Reference Manual

2.2. Processor Pipeline

The Nios V/m processor employs a five-stage pipeline.

Table 5.  Processor Pipeline Stages
Stage Denotation Function
F Instruction fetch
  • PC+4 calculation
  • Next instruction fetch
  • Pre-decode for register file read
D Instruction decode
  • Decode the instruction
  • Register file read data available
  • Hazard resolution and data forwarding
E Instruction execute
  • ALU operations
  • Memory address calculation
  • Branch resolution
  • CSR read/write
M Memory
  • Memory and multicycle operations
  • Register file write
  • Branch redirection
W Write back
  • Facilitates data dependency resolution by providing general-purpose register value.

The Nios® V/m processor implements the general-purpose register file using the M20K memory blocks. The processor takes one processing cycle to read from an M20K location. Therefore, the F-stage initiates register file reads so general-purpose register values are available in D-stage.

Writing to the M20K location takes two processing cycles. Therefore, the M-stage initiates writes to a general-purpose register. If there is a dependency to resolve, the M-stage carries forward the value to the W-stage.

The core resolves data dependencies in the D-stage. Operands can move from register file read or E-stage, M-stage, or W-stage.

Reasons for the pipeline stalling:
  • Data dependency—if the source operand is not available in D-stage, instruction in D-stage and F-stage stalls until the operand becomes available. The scenario can happen if destination general-purpose register of load or multicycle instruction in E-stage or M-stage is the source for instruction in D-stage.
  • Resource stall—if a memory operation or multicycle is pending in M-stage, the instructions in preceding stages stalls until M-stage completes the instruction.
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