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Ixiasoft
2.3.7.1.3. Address Map
The address map for memories and peripherals in a Nios® V/m processor system is design dependent. The following addresses are part of the processor:
- Reset Address
- Debug Exception Address
- Exception Address
- Timer and Software Interrupt Address
You can specify the Reset Address and Debug Exception Address in Platform Designer during system configuration. You can modify the Exception Address stored in the mvtec register. mvtime and mtimecmp register controls the timer interrupt. The msip register bit controls the software interrupt.