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Ixiasoft
2.3.7.1.2. Data Manager Port
The Nios® V/m processor data bus is implemented as a 32-bit AMBA* 4 AXI manager port. The data manager port performs two functions:
- Read data from memory or a peripheral when the processor executes a load instruction.
- Write data to memory or a peripheral when the processor executes a store instruction.
axsize signal value indicates the load/store instruction size- byte (LB/SB), halfword (LH/SH) or word (LW/SW). Address on axaddr signal is always aligned to size of the transfer. For store instructions, respective writes strobe bits are asserted to indicate bytes being written.
Nios® V/m processor core does not support speculative issue of load/store instruction. Hence, a core can issue only one load or store instruction and waits until the issued instruction is complete.
Interface | Signal | Role | Direction |
---|---|---|---|
Write Address Channel | awaddr | Store address | Output |
awprot | Undefined- constant value | Output | |
awvalid | Store valid | Output | |
awsize | Store size- SB, SH, SW | Output | |
awready | From memory/interconnect | Input | |
Write Data Channel | wvalid | Store valid | Output |
wdata | Store data | Output | |
wstrb | Byte position in word | Output | |
wlast | Constant 1 | Output | |
wready | From memory/interconnect | Input | |
Write Response Channel | bvalid | Store done | Input |
bresp [1:0] | Store done status: Non-zero value denotes store access fault exception. | Input | |
bready | Constant 1 | Output | |
Read Address Channel | araddr | Load Address | Output |
arprot | Undefined- constant value | Output | |
arvalid | Load Valid | Output | |
arsize | Load size: LB, LH, LW | Output | |
arready | From subordinate/interconnect | Input | |
Read Data Channel | rdata | Read data | Input |
rvalid | Read data valid | Input | |
rresp | Load response status: Non-zero value denotes load access fault exception. | Input | |
rready | Constant 1 | Output |