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Ixiasoft
1.5.1. Install the Design Files
1.5.2. Analyze System Requirements
1.5.3. Start the Software and Open the Example Project
1.5.4. Create a New System
1.5.5. Define the System in
1.5.6. Integrate the System into the Project
1.5.7. Download the Hardware Design to the Target FPGA
1.5.8. Develop Software Using the SBT for Eclipse
1.5.9. Run the Program on Target Hardware
1.5.5.1. Specify Target FPGA and Clock Settings
1.5.5.2. Add the On-Chip Memory
1.5.5.3. Add the Processor Core
1.5.5.4. Add the JTAG UART
1.5.5.5. Add the Interval Timer
1.5.5.6. Add the System ID Peripheral
1.5.5.7. Add the PIO
1.5.5.8. Specify Base Addresses and Interrupt Request Priorities
1.5.5.9. Generate the System
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Ixiasoft
1.5.6.5. Set Timing
To ensure the design meets timing, perform the following steps:
- On the File menu, click Open.
- In the Files of type list, select Script Files (*.tcl, *.sdc, *.qip).
- Browse to locate <design files directory>/hw_dev_tutorial.sdc and click Open. The file opens in the text editor.
- Locate the following create_clock command:create_clock -name sopc_clk -period 20 [get_ports PLD_CLOCKINPUT]
- Change the period setting from 20 to the clock period (1/frequency) in nanoseconds of the oscillator driving the clock pin.
- On the File menu, click Save.
- On the Assignments menu, click Settings.
The Settings dialog box appears.
- Under Category, click TimeQuest Timing Analyzer.
- Next to File name, click the browse (...) button.
- Browse to locate <design files directory>/hw_dev_tutorial.sdc and click Open to select the file.
- Click Add to include hw_dev_tutorial.sdc in the project.
- Turn on Enable multicorner timing analysis during compilation.
- Click OK.