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1.5.1. Install the Design Files
1.5.2. Analyze System Requirements
1.5.3. Start the Software and Open the Example Project
1.5.4. Create a New System
1.5.5. Define the System in
1.5.6. Integrate the System into the Project
1.5.7. Download the Hardware Design to the Target FPGA
1.5.8. Develop Software Using the SBT for Eclipse
1.5.9. Run the Program on Target Hardware
1.5.5.1. Specify Target FPGA and Clock Settings
1.5.5.2. Add the On-Chip Memory
1.5.5.3. Add the Processor Core
1.5.5.4. Add the JTAG UART
1.5.5.5. Add the Interval Timer
1.5.5.6. Add the System ID Peripheral
1.5.5.7. Add the PIO
1.5.5.8. Specify Base Addresses and Interrupt Request Priorities
1.5.5.9. Generate the System
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1.5.5.9. Generate the System
To generate the system, perform the following steps:
- Click the Generation tab.
- Select None in both the Create simulation model and Create testbench system lists.
Because this tutorial does not cover the hardware simulation flow, you can select these settings to shorten generation time.
- Click Generate. Click Yes when the Save changes? dialog box appears.
- Type first_nios2_system in the File name box and click Save.
The Generate dialog box appears and system generation process begins. The generation process can take several minutes. When generation completes, prompt: Create HDL design files for synthesis.
- Click Close to close the dialog box.
- On the File menu, click Exit to close and return to the software.
You are ready to integrate the system into the hardware project and use the SBT for Eclipse to develop software.