AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller

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ID 683601
Date 9/22/2017
Public
Document Table of Contents
Document Table of Contents x
1. AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller
1. AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller x
1.1. ULPI Signals 1.2. HPS USB Controller Timing Characteristics 1.3. PHY Selection 1.4. Implementing Input Clock Mode with FPGA Clock Source 1.5. Revision History
1.2. HPS USB Controller Timing Characteristics x
1.2.1. USB Controller Timing Requirements 1.2.2. USB Controller Setup and Hold Relationships
1.3. PHY Selection x
1.3.1. USB PHY Timing Characteristics 1.3.2. Output Clock Mode 1.3.3. Input Clock Mode
1.3.1. USB PHY Timing Characteristics x
1.3.1.1. USB Setup and Hold Relationships 1.3.1.2. USB Controller to PHY Setup and Hold Timing Arcs 1.3.1.3. USB PHY to Controller Setup and Hold Timing Arcs
1.3.1.2. USB Controller to PHY Setup and Hold Timing Arcs x
1.3.1.2.1. USB Controller to PHY Setup Timing Analysis 1.3.1.2.2. USB Controller to PHY Hold Timing Analysis
1.3.1.3. USB PHY to Controller Setup and Hold Timing Arcs x
1.3.1.3.1. USB PHY to Controller Setup Timing Analysis 1.3.1.3.2. USB PHY to Controller Hold Timing Analysis
1.3.3. Input Clock Mode x
1.3.3.1. External Clock Source 1.3.3.2. FPGA Clock Source
1.4. Implementing Input Clock Mode with FPGA Clock Source x
1.4.1. Configuring the HPS USB 2.0 OTG Controller 1.4.2. Select the Controller Clock as Loan I/O 1.4.3. Connecting the Clock in the Top Level Design
1. AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller

1.3.1.3.2. USB PHY to Controller Hold Timing Analysis

To determine if your configuration meets hold timing requirements at the USB controller, you must calculate the worst case hold time to verify that it falls within limits. To meet hold time requirements, the data must arrive and be held for longer than the data hold requirement. The inequality below evaluates the data arrival and data required time using values in USB Controller and PHY timing characteristic USB Controller and PHY, respectively. By replacing each side of the inequality with the timing expressions that represent data arrival and data required time, you can verify if the hold timing requirements are met. 
Data Arrival ≥ Data Required

LaunchEdge + PHY Td_min + DTrace Td_min ≥ LatchEdge + ClkTrace Td_max + MAC Th

If you assume that the LaunchEdge = 0 ns and the LatchEdge = 0 ns, then the equation can be simplified and you can verify that the hold time is within limits: 

PHY Td_min + DTrace Td_min - ClkTrace Td_max  ≥  MAC Th

2.0 + 0.05 - 0.1 ≥ 1.0

1.95 ns ≥ 1.0 ns
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