AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller

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ID 683601
Date 9/22/2017
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Document Table of Contents
Document Table of Contents x
1. AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller
1. AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller x
1.1. ULPI Signals 1.2. HPS USB Controller Timing Characteristics 1.3. PHY Selection 1.4. Implementing Input Clock Mode with FPGA Clock Source 1.5. Revision History
1.2. HPS USB Controller Timing Characteristics x
1.2.1. USB Controller Timing Requirements 1.2.2. USB Controller Setup and Hold Relationships
1.3. PHY Selection x
1.3.1. USB PHY Timing Characteristics 1.3.2. Output Clock Mode 1.3.3. Input Clock Mode
1.3.1. USB PHY Timing Characteristics x
1.3.1.1. USB Setup and Hold Relationships 1.3.1.2. USB Controller to PHY Setup and Hold Timing Arcs 1.3.1.3. USB PHY to Controller Setup and Hold Timing Arcs
1.3.1.2. USB Controller to PHY Setup and Hold Timing Arcs x
1.3.1.2.1. USB Controller to PHY Setup Timing Analysis 1.3.1.2.2. USB Controller to PHY Hold Timing Analysis
1.3.1.3. USB PHY to Controller Setup and Hold Timing Arcs x
1.3.1.3.1. USB PHY to Controller Setup Timing Analysis 1.3.1.3.2. USB PHY to Controller Hold Timing Analysis
1.3.3. Input Clock Mode x
1.3.3.1. External Clock Source 1.3.3.2. FPGA Clock Source
1.4. Implementing Input Clock Mode with FPGA Clock Source x
1.4.1. Configuring the HPS USB 2.0 OTG Controller 1.4.2. Select the Controller Clock as Loan I/O 1.4.3. Connecting the Clock in the Top Level Design
1. AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller

1.3.3.2. FPGA Clock Source

When the FPGA fabric drives the USB Controller clock output the USB interface requires the use of a loan I/O pin instead of the typical USB clock input pin.

User logic in the FPGA drives a clock signal, typically derived from a PLL, into the loan I/O assigned to the USB controller. This clock signal routes into the USB controller and externally to the USB PHY. This configuration provides a common clock source for both the USB controller and PHY much like when the PHY is configured for input clock mode with an external clock source. Because this mode of operation differs from the previous examples, you must configure the USB controller for SDR with PHY clock input mode in the Peripheral Pins tab of the HPS Parameters window of Platform Designer (Standard).

Figure 6. USB PHY in Input Clock Mode with FPGA PLL Clock Source
Note: When implementing input clock mode with an FPGA clock source, the FPGA must be configured prior to USB interface operation. This implementation can impact embedded software significantly and must be considered carefully before selecting the input clock mode with FPGA clock source. Using an external clock source (as shown in Figure 5) can accomplish the same objective without necessarily affecting embedded software.
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