AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller

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ID 683601
Date 9/22/2017
Public
Document Table of Contents
Document Table of Contents x
1. AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller
1. AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller x
1.1. ULPI Signals 1.2. HPS USB Controller Timing Characteristics 1.3. PHY Selection 1.4. Implementing Input Clock Mode with FPGA Clock Source 1.5. Revision History
1.2. HPS USB Controller Timing Characteristics x
1.2.1. USB Controller Timing Requirements 1.2.2. USB Controller Setup and Hold Relationships
1.3. PHY Selection x
1.3.1. USB PHY Timing Characteristics 1.3.2. Output Clock Mode 1.3.3. Input Clock Mode
1.3.1. USB PHY Timing Characteristics x
1.3.1.1. USB Setup and Hold Relationships 1.3.1.2. USB Controller to PHY Setup and Hold Timing Arcs 1.3.1.3. USB PHY to Controller Setup and Hold Timing Arcs
1.3.1.2. USB Controller to PHY Setup and Hold Timing Arcs x
1.3.1.2.1. USB Controller to PHY Setup Timing Analysis 1.3.1.2.2. USB Controller to PHY Hold Timing Analysis
1.3.1.3. USB PHY to Controller Setup and Hold Timing Arcs x
1.3.1.3.1. USB PHY to Controller Setup Timing Analysis 1.3.1.3.2. USB PHY to Controller Hold Timing Analysis
1.3.3. Input Clock Mode x
1.3.3.1. External Clock Source 1.3.3.2. FPGA Clock Source
1.4. Implementing Input Clock Mode with FPGA Clock Source x
1.4.1. Configuring the HPS USB 2.0 OTG Controller 1.4.2. Select the Controller Clock as Loan I/O 1.4.3. Connecting the Clock in the Top Level Design
1. AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller

1.3.1. USB PHY Timing Characteristics

Before selecting a USB PHY and clock mode of operation, you should perform a timing analysis of the USB controller and PHY.

If the USB PHY supports input and output clock modes with different timing characteristics, perform a timing analysis of both modes before making a selection. This document includes a detailed timing analysis example of a MicroChip USB3300 PHY in output clock mode.

Table 3.  USB PHY Timing CharacteristicsThe PHY timing characteristics listed below are from the MicroChip USB3300 PHY that populates both the Arria® V and Cyclone® V SoC Development Boards. On the development board, this USB PHY operates in output clock mode.
Note: In the Arria® V and Cyclone® V SoC devices, the USB controller does not support PHYs using link power management (LPM) mode. It is recommended that designers use the MicroChip SB3300 PHY device that is verified on the development board.
Symbol

Description

Min

Typ

Max

Units

PHY Tsu PHY setup time for USB_STP/USB_DATA[7:0]

5.0

 - -

ns

PHY Th PHY hold time for USB_STP/USB_DATA[7:0] 0 - -

ns

PHY Td Output delay for USB_DIR/USB_NXT/USB_DATA[7:0]

2.0

- 5.0

ns

ClkTrace Td Clock Trace delay

0.05

 - 0.1

ns
DTrace Td

Data Trace delay

0.05

 - 0.1

ns
Clock Tu

Clock Source Uncertainty

 - 0.3 -

ns
The clock source uncertainty (Clock Tu) parameter is a board-level guard band factor that models period uncertainty on the PHY's clock caused by clock source inaccuracies and jitter. You may modify this value based on your application. The following guidelines apply when using this parameter:
  • For setup analysis, use Clock Tu to model period uncertainty in the launch-to-latch edge setup relationship.
  • Do not use Clock Tu for hold analysis because the launch and latch edges are the same physical clock edge in time.

For this timing analysis example, assume the trace lengths of the DATA[7:0], STP and NXT signals are matched when verifying if the USB timing is met off-chip.


Section Content
USB Setup and Hold Relationships
USB Controller to PHY Setup and Hold Timing Arcs
USB PHY to Controller Setup and Hold Timing Arcs

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